WM8960 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8960' PDF : 91 Pages View PDF
WM8960
Production Data
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8960 uses stereo 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback
and high oversampling rates reduce the effects of jitter and high frequency noise. The ADC Full Scale
input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0Vrms. Any
voltage greater than full scale may overload the ADC and cause distortion.
The ADCs are enabled by the ADCL/R register bit.
REGISTER
ADDRESS
R25 (19h)
Power
management (2)
BIT LABEL
3
ADCL
2
ADCR
Table 8 ADC Enable Control
DEFAULT
DESCRIPTION
0
Enable ADC left channel:
0 = ADC disabled
1 = ADC enabled
0
Enable ADC right channel:
0 = ADC disabled
1 = ADC enabled
The polarity of the output signal can be changed under software control using the ADCPOL[1:0]
register bits. The DATSEL bits are used to select which channel is used for the left and right ADC
data.
REGISTER
ADDRESS
R5 (05h)
ADC and DAC
Control (1)
BIT
LABEL
6:5 ADCPOL[1:0]
R23 (17h)
3:2 DATSEL
Additional Control
[1:0]
(1)
Table 9 ADC Control
DEFAULT
DESCRIPTION
00
ADC polarity control:
00 = Polarity not inverted
01 = ADC L inverted
10 = ADC R inverted
11 = ADC L and R inverted
00
ADC Data Output Select
00: left data = left ADC;
right data =right ADC
01: left data = left ADC;
right data = left ADC
10: left data = right ADC;
right data =right ADC
11: left data = right ADC;
right data = left ADC
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally amplified or attenuated over a range from –97dB to +30dB in
0.5dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit
code X is given by:
0.5 (X-195) dB for 1 X 255;
MUTE for X = 0
The ADCVU control bit controls the loading of digital volume control data. When ADCVU is set to 0,
the LADCVOL or RADCVOL control data will be loaded into the respective control register, but will not
actually change the digital gain setting. Both left and right gain settings are updated when ADCVU is
set to 1. This makes it possible to update the gain of both channels simultaneously.
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PD, August 2013, Rev 4.2
26
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