XR16C864 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C864' PDF : 51 Pages View PDF
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
REV. 2.2.0
EMSR[3]: Receive Direct Memory Access Request Enable
Logic 0 = Normal.
Logic 1 = Enable RX Direct Memory Access Request. See DACK, TC, AEN, TXDRQ and RXDRQ pin
descriptions for details.
EMSR[5:4]: Extended RTS Hysteresis
TABLE 15: AUTO RTS HYSTERESIS
TABLE 16:
EMSR EMSR
BIT-5 BIT-4
FCTR
BIT-1
FCTR
BIT-0
RTS#
HYSTERESIS
(CHARACTERS)
0
0
0
0
0
0
0
0
1
±4
0
0
1
0
±6
0
0
1
1
±8
0
1
0
0
±8
0
1
0
1
±16
0
1
1
0
±24
0
1
1
1
±32
1
0
0
0
±40
1
0
0
1
±44
1
0
1
0
±48
1
0
1
1
±52
1
1
0
0
±12
1
1
0
1
±20
1
1
1
0
±28
1
1
1
1
±36
EMSR[7:6]: Reserved
4.12 FIFO Level Register (FLVL) - Read-Only
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this
is not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 14 for details.
36
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