XR82C684
Table 1 (('% ' ' (% I( 3( 3
,(%% %% '( 3( ' * %
,(% (% (% / ,(%1 ( (
' (-%&% 3 55 ' ( (%
/ ((, 1 ' ,(% Please note that
the suffix “n” is used at the end of many of the QUART
registers symbols in order to refer, generically, to any one
of the four channels ; 3# ' % *
( 3( % (* * %% * ,(%
* ,(%# ((& * 3(, &
E( ''%% ,(% ( 3(
' ( / ( 1 ,(% ( 3
% ''% ( /55 +$:51 '
% ( 6 /55 +$:51
' ' (%% & 3((, (
( ' K% ,(%
* # ,(%%# 3( ( ,( ' #
% ,(' %% *%
*'( % * ' &
,(%% (%'%% ( ( ( Section G.3
B.2 Command Decoding
5' ' (% I( 3( ,(% $
,# * % ,(%%
-(% %(# -(%
'(# , 3( *'(((, %(% *
(%' % ' ' ( ' %
( * * ' ,(% (% % 3
CRA, CRB, CRC, CRD
Bit 7
Bit 6
Bit 5
Miscellaneous Commands
3(, "
Bit 4
Bit 3
Bit 2
Enable/Disable Receiver
L : ,
L 5 "
L !(% "
L : ( %
Bit 1
Bit 0
Enable/Disable Transmitter
L : ,
L 5 "
L !(% "
L : >( ! %
*'( * 3 ( *
,(%% (% *(& %(, * 3 (% ( (% %
( (% %( - '(
( * ,(% (% %
( 6 %(% * (%' % ' % Table 2
*(% ' % %% '( 3( ( *
,(%% Please note that the upper nibble
commands 116 through B effects only the performance of
Command Register’s Channel. However, commands C
and D effects system (or chip) level operation.
Bit 7
Bit 6
Bit 5
Bit 4
Description
Null Command:
Reset MRn Pointer: %% K% ( (
Reset Receiver: % ((( ' '( % (* ;3 % %
( '( (% (% $ (% *%
Reset Transmitter: %% ((( ' %( % (* ;3
% ( 8! (% * ' (,
Reset Error Status: % '( )6 )# +(& 5 +5# (,
5 5 5 5 %% (%# PB74Q
'(*('&# (* 5 # * (' ' (% % /) '61 5 #
(% ' 3( % * '( 5 $(' % ( % ,(% $
) '6 5 # ' ( +5# 5# 5# ) ''%# 3( '
( *,, ( % ,(%# ( (% ' (% (%%
$* 5 # * (' ' (% % / ' 5 1#
' % * % ,(% * +5# 5# ) *' ' ' &
' ' %(% $ / ' 5 1# % * % ((' % (%
% & ' ' (% * ;
: 7 5 ((' (% 3&% % % /) '6 5 1 ((' #
I(% (% ' %
Reset Break Change Interrupt: % ' K% 6 ' , ( %%
(# 3( ( ( $ % ,(%
0