XR82C684CJ-F View Datasheet(PDF) - Exar Corporation

Part Name

Description

MFG CO.

XR82C684CJ-F

CMOS Quad Channel UART (QUART)

Exar Corporation 

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XR82C684

6(,   *    " ' ' $*  ' ' (%

3((, (    '% ;) (% *#  (% ( 3(  %

,( *    ( # 3    ' ' (%

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Note: If this bit is configured to reflect the FFULLB

indicator, this bit will not be set (nor will produce an

interrupt request) if one or two characters are still

remaining in RHRB, following data reception. Hence, it is

possible that the last two characters in a string of data

(being received) could be lost due to this phenomenon.

ISR1[4] TXRDYB - Channel B Transmitter Ready

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+ 3(%  3 ' '  ;).

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ISR1[3] Counter #1 Ready

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- D 
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-(% '  *  ( Section D

ISR1[2]: Delta Break A - Channel A Change in

Break

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ISR1[1] RXRDYA/FFULL A - Channel A Receiver

Ready or FIFO Full

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P.Q $*  (% ( *( (% ' *(,  *'( %  

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+  (% ( (% %

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+ %   / %1 ; $*

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+ % ; $*  ' ' (%

3((, (    '% ; (% *#  (% ( 3(  %

,(# *  3(,    ( # 3    ' ' (%

  ( ;

Note: If this bit is configured to reflect the FFULLA

indicator, this bit will not be set (nor will produce an

interrupt request) if one or two characters are still

remaining in RHRA, following data reception. Hence, it is

possible that the last two characters in a string of data

(being received) could be lost due to this phenomenon.

Therefore, the user is advised to read RHRA until empty.

ISR1[0]: Channel A Transmitter Ready

 (% ( (%  (' * 8!H # PQ

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&  ''  ' ' *   
+   ( (%

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+ 3(%  3 ' '  ;.

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C.1.2 ISR2 Register - Channels C and D

ISR2[7]: Input Port Change of State:

$*  (% ( (%    ,(' /1#    ' , * % 3%

'  $ +  (% $+0  $+   % %('%

 (% ( & (,   $+
 (* $PBQ L 

$PBQ (% ' 3   
+ %    $ + 

*(,( ,(% $+
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#

  % 3( (7

   ((( $ +  (   ' , %

 



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