XR82C684J-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR82C684J-F' PDF : 107 Pages View PDF
XR82C684
External Vectored Interrupt Processing (Interrupt
Mode 0)
? 0 • + 3( ( (% ( (* /$ 1
(% '( % " ' E $: ( (%
%% & ( (' I %(, ( #
+ 3( ' (% ' (% '( *
' ( * (% (% '( # + 3( %%
$: ,, / 31 $: (% '( 3 /$
'6 3 , 1 %(, + % (
((( ' %% * ( % ('(, E
? 0 + % ( $ # ( (%
3((, / ' (* ( 1 ! )%# * 3(,
%% ( * $: $ (% '% * (% (
# (% / ' 1 (* ( (% ' * *
5 (% '( % ? 0 +
% % (, (** (% '( %
40; % (% '( % & ' %
% '(*(' '( % 3( ( +K% & %' # 3
( $ % (' ( %( % Table 9
% % (% * % 5 (% '( %#
' % ' % (, 5 %% %
Op-Code (hex)
Mnemonic
Restart
Address (hex)
B
0
0
!B
!
0
0
5B
;
5
0;
0
B
4;
4
40;
40
Table 9. Z-80 CPU Restart Instructions
Used with Vectored Interrupts (Mode 0)
* # ' + ' ( % ' * *
% 5 (% '( %# ( 3( ,( " '(, (%
(% '( & (, + , 3(
( / % 1 %% * 3 %# ,
' 3( ' / % %%1 '(
" # (* ' 5B. (% !
)% (, $: '&' # (% ' ' % % 3(
; (% '( # + 3( .
( , ' , ' 3( '
'( ( & % Table 9 % (%
% %( * (% (, ( % (' (
,(% (% '( ( &
" * '( '( (J(, (% * * (
' %%(,# 3 ( ( *'(, # (% %
( Section C.6.2.3 (% % '( (%'%% % ( *'(,
00 + (% "' %
' ' % 3( ? 0 +# (
(% (, ( $ ? 0 (%
(, ( $
Direct Interrupt Processing (Interrupt Mode 1)
? 0• + 3( ( (% ( (* /$ 1
(% '( % " ' E $: ( (%
%% & ( (' I %(, ( #
+ 3( ' (% ' (% '( * 3 %#
, ' 3( (' & 3(
& '( ( & '( '( %(, *
? 0 + (' , ' 3(
' '( ( %&% & $ (% '% #
, ' 3 ' 40. ( &
% (% % %( * (% (, (
( % (' ( (% (' '( (
& ? 0 + % (
( (' 3( & % * /$
'6 3 , 1 + C% ' %% % ,
$ (' ( # (( % '% % *
( I % % (
Peripheral Vectored Interrupt Processing (Interrupt
Mode 2)
? 0 • + 3( ( (% ( (* /$ 1
(% '( % " ' (% ( / 1 (%
& % * (* % 3(% % ' ' (
I % % * % ( % $:
( * ? 0 + (% ( 3%
( (, (' ( (*& (% * ' ( ( # C%
( ( % ('(,
E $: ( (% %% & ( ('
I %(, ( # + 3( ' ( '
(% ' (% '( ' (% ' (% '( (%
' # + 3( %% $: %(,
(* ( (' ( % (' (%
,( ' ( (, ( (' %
' $: % # ( 3( ' /( ' 1
! )% (% ( ' 3( &
+ + 3( ' , '
'( * & ( ' Please note
that if the IEI input to the QUART (or Zilog peripheral
device) is “low” then the QUART (or Zilog peripheral
device) will be disabled from generating any interrupt
requests to the CPU.
" * (% ' (% % 3 (
Figure 23 $ (% '% 80.0@ (%
@0
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