XR82C684J-F View Datasheet(PDF) - Exar Corporation

Part Name

Description

MFG CO.

XR82C684J-F

CMOS Quad Channel UART (QUART)

Exar Corporation 

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XR82C684

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Table 10. The Relationship Between the Contents of the Interrupt Vector Registers (of the QUART)

and the Location of the Interrupt Service Routine (Z-80 CPU)

Note: The LSB of the IVR is always set to “0” once read by the CPU. Interrupt Service Routines must begin at even addresses.

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XR82C684

Figure 23. Schematic of an Approach to Interface the QUART to the Z-80 CPU (for Z-Mode Operation)

 

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