XRT4500 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT4500' PDF : 96 Pages View PDF
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.5
áç
FIGURE 27. ILLUSTRATION OF THE DCE/DTE INTERFACE, WITH THE DCE MODE XRT4500 OPERATING IN THE “2-
CLOCK” MODE
SCC (L)
TXD
SCTE
TXC_IN
RXC_IN
RXD_IN
DTE
60
TX1
63
TXD
78
62
79
64
77
67
TX2
65
76
70
TXC
70
73
RX3
71
71
77
RXC
64
74
RX2
76
65
78
RXD
63
1
RX1
79
62
XRT4500
DCE
RX1
1
74
RX2
68
TX3
67
TX2
60
TX1
XRT4500
SCC (R)
TXD_IN
SCTE_IN
TXC
RXC
RXD
In this case, the “2-Clock” Mode offers a considerable
amount of design flexibility. This approach permits the
“DCE Equipment” System Design Engineer to design
and layout a board that can be automatically config-
ured to support either the “3-Clock” Mode (if all three
clock signals are present, over the DTE/DCE Inter-
face). Further, this approach also permits the System
Design Engineer to configure the XRT4500 into the
“2-Clock” Mode (if the SCTE clock signal is not
present). This feature is a nice alternative to “hard-
wiring” the “TXC” output (of the DCE SCC) to the
“SCTE” input.
NOTE: The “2-Clock” Mode feature, by itself, does not solve
the “2-Clock/Propagation Delay” phenomenon. However,
the “2-Clock” Mode, within the XRT4500, permits the user
to do the following.
a. To configure the XRT4500 to automatically operate
in the “3-Clock” Mode, whenever it is interfaced to a
DTE that supports all three (3) clock signals, or
b. To configure the XRT4500 to automatically operate
in the “2-Clock” Mode, whenever it is interfaced to a
DTE that only supports two (2) clock signals. Once
the user has configured the XRT4500 to operate in
the “2-Clock” Mode, then the user can “solve” the “2-
Clock/Propagation Delay” phenomenon by invoking
the “Clock Inversion” feature, as described below in
Section 1.2.6.
Configuring the “2-Clock” Mode.
The user can configure the XRT4500 to operate in
the “2-Clock” Mode by setting the “2CK/3CK” input
pin “high”. Conversely, the user can disable the “2-
Clock” Mode (otherwise known as operating the
XRT4500 in the “3-Clock” Mode) by setting the “2CK/
3CK” input pin “low”.
1.3.6 The “Clock Inversion” (CK_INV) feature
The XRT4500 can be configured to invert the “TXC”
signal by setting the “CK_IN” input pin (pin 54) “low”.
Setting the “CK_INV” input to “high” removes the in-
vert from the “TXC” signal path. An illustration of the
“DCE Mode” XRT4500, configured to invert the “TXC”
signal is illustrated in Figure 28.
55
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