XRT72L13 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT72L13' PDF : 370 Pages View PDF
áç
PRELIMINARY
PIN DESCRIPTIONS
PIN #
NAME
51
RxDS1Data_5
RxHDLC_Data_5
52
RxDS1Clk_5
53
RxDS1Data_4/
RxHDLC_Data_4
54
RxDS1Clk_4
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
TYPE
O
O
O
O
DESCRIPTION
Receive DS1/E1 Data Output - Channel 5/Receive HDLC Control-
ler Block Output - Bit 5:
The funtion of this output pin depends upon whether the XRT72L13 is
operating in the "Multiplexer/De-Multiplexer" Mode or in the "High
Speed HDLC Controller" Mode.
Receive DS1/E1 Data Output - Channel 5: (Multiplexer/De-Multi-
plexer Mode):
This pin outputs either a DS1 or E1 signal from the M12 multiplexer.
Each bit, within the DS1 or E1 data stream is output upon the rising
edge of RxDS1Clk_5.
Receive HDLC Controller Block Output - Bit 5: (High Speed HDLC
Controller Mode)
This output pin along with RxHDLC_Data[0:4] and
RxHDLC_Data[6:7] output the contents of all HDLC frames that have
been received (via the DS3 payload) from the remote terminal equip-
ment.
The data on this output pin is updated upon the rising edge of "RxH-
DLCClk".
NOTE: This pin is inactive while the Receive HDLC Controller is
receiving the "Flag Sequence" octet.
Receive DS1/E1 Clock Output - Channel 5:
This pin outputs either a DS1 (1.544MHz) or an E1 (2.048MHz) clock
signal to the Terminal Equipment. The XRT72L13 will update the data
on the "RxDS1Data_5" line, upon the rising edge of this signal.
Receive DS1/E1 Data Output - Channel 4/Receive HDLC Control-
ler Block Output - Bit 4:
The funtion of this output pin depends upon whether the XRT72L13 is
operating in the "Multiplexer/De-Multiplexer" Mode or in the "High
Speed HDLC Controller" Mode.
Receive DS1/E1 Data Output - Channel 4: (Multiplexer/De-Multi-
plexer Mode):
This pin outputs either a DS1 or E1 signal from the M12 multiplexer.
Each bit, within the DS1 or E1 data stream is output upon the rising
edge of RxDS1Clk_4.
Receive HDLC Controller Block Output - Bit 4: (High Speed HDLC
Controller Mode)
This output pin along with RxHDLC_Data[0:3] and
RxHDLC_Data[5:7] output the contents of all HDLC frames that have
been received (via the DS3 payload) from the remote terminal equip-
ment.
The data on this output pin is updated upon the rising edge of "RxH-
DLCClk".
NOTE: This pin is inactive while the Receive HDLC Controller is
receiving the "Flag Sequence" octet.
Receive DS1/E1 Clock Output - Channel 4:
This pin outputs either a DS1 (1.544MHz) or an E1 (2.048MHz) clock
signal to the Terminal Equipment. The XRT72L13 will update the data
on the "RxDS1Data_4" line, upon the rising edge of this signal.
9
Share Link: 
