XRT72L13 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT72L13' PDF : 370 Pages View PDF
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
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PRELIMINARY
PIN DESCRIPTIONS
PIN #
55
NAME
RxDS1Data_3/
RxHDLC_Data_3
56
RxDS1Clk_3/
RxIDLE
TYPE
O
O
DESCRIPTION
Receive DS1 Data Output - Channel 3/Receive HDLC Controller
Block Output - Bit 3
The funtion of this output pin depends upon whether the XRT72L13 is
operating in the "Multiplexer/De-Multiplexer" Mode or in the "High
Speed HDLC Controller" Mode.
Receive DS1 Data Output - Channe1 3 (Multiplexer/De-Multi-
plexer Mode)
This pin outputs a DS1 signal from the M12 de-multiplexer. Each bit,
within the DS1 data stream is output upon the rising edge of
RxDS1Clk_3.
NOTES:
1. This output pin is inactive if the corresponding M12 DEMUX is
de-multiplexing an ITU-T G.747 data stream.
2. This pin will output the contents of DS2 channel # 1, if M12
MUX # 1 is bypassed.
Receive HDLC Controller Block Output - Bit 3 (High Speed HDLC
Controller Mode)
This output pin along with RxHDLC_Data[0:2] and
RxHDLC_Data[4:7] output the contents of all HDLC frames that have
been received (via the DS3 payload) from the remote terminal equip-
ment.
The data on this output pin is updated upon the rising edge of "RxH-
DLCClk".
NOTE: This pin is inactive while the Receive HDLC Controller is
receiving the "Flag Sequence" octet.
Receive DS1 Clock Output - Channel 3/Receive Idle (Flag
Sequence) Indicator Output:
The funtion of this output pin depends upon whether the XRT72L13 is
operating in the "Multiplexer/De-Multiplexer" Mode or in the "High
Speed HDLC Controller" Mode.
Receive DS1 Clock Output - Channel 3 (Multiplexer/De-Multi-
plexer Mode):
This pin outputs a DS1 (1.544MHz) clock signal to the Terminal
Equipment. The XRT72L13 will update the data on the
"RxDS1Data_3" line, upon the rising edge of this signal.
NOTES:
1. This output pin is inactive if the corresponding M12 DEMUX is
de-multiplexing an ITU-T G.747 data stream.
2. This pin will output a DS2 rate clock signal (6.312MHz) if M12
# 1 is bypassed.
RxIDLE - Receive Idle (Flag Sequence) Indicator Output (High
Speed HDLC Controller Mode):
The Receive HDLC Controller block will drive this output pin "high"
any time it is receiving a continuous stream of the "Flag Sequence"
octet (0x7E) via the DS3 payload.
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