XRT7300IV View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT7300IV' PDF : 55 Pages View PDF
XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
áç
Whenever the XRT7300 delivers Dual-Rail format to
the Terminal Equipment it does so via the following
output signals.
• RPOS
• RNEG
• RCLK1
• RCLK2
Figure 23 illustrates the typical interface for the trans-
mission of data in a Dual-Rail Format from the Re-
ceive Section of the XRT7300 to the Receiving Termi-
nal Equipment.
FIGURE 23. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE
RECEIVE SECTION OF THE XRT7300 TO THE RECEIVING TERMINAL EQUIPMENT
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
RxPOS
RxNEG
RCLK1, 2
RPOS
RNEG
Receive
Logic
RCLK1, 2 Block
Exar E3/DS3/STS-1 LIU
The manner that the LIU transmits Dual-Rail data to
the Receiving Terminal Equipment is described below
and illustrated in Figure 24. The XRT7300 typically
updates the data on the RPOS and RNEG output
pins on the rising edge RCLK1 (or RCLK2).
FIGURE 24. HOW THE XRT7300 OUTPUTS DATA ON THE RPOS AND RNEG OUTPUT PINS
RPOS
RNEG
RCLK1
RCLK1 (or RCLK2) is the Recovered Clock signal
from the incoming Received line signal. As a result,
these clock signals are typically 34.368 MHz for E3
applications, 44.736 MHz for DS3 applications and
51.84 MHz for SONET STS-1 applications.
In general, if the XRT7300 received a positive-polarity
pulse in the incoming line signal via the RTIP and
RRING input pins, then the XRT7300 pulses the
RPOS output pin “High”. If the XRT7300 received a
negative-polarity pulse in the incoming line signal via
the RTIP and RRING input pins, then the XRT7300
pulses the RNEG output pin “High”.
Inverting the RCLK1 or RCLK2 outputs
When using the XRT7300, either of the RCLK1 or
RCLK2 signals can be inverted with respect to the de-
livery of the RPOS and RNEG output signals to the
Receiving Terminal Equipment. This feature may be
useful for those customers whose Receiving Terminal
Equipment logic design is such that the RPOS and
RNEG data must be sampled on the rising edge of
RCLK1 or RCLK2. Figure 25 illustrates the behavior
34
Share Link: 
