XRT7300IV View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT7300IV' PDF : 55 Pages View PDF
XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
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FIGURE 26. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A SINGLE-RAIL FORMAT FROM THE
RECEIVE SECTION OF THE XRT7300 TO THE RECEIVING TERMINAL EQUIPMENT
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
RxPOS
RCLK1, 2
RPOS
RCLK1, 2
Receive
Logic
Block
Exar E3/DS3/STS-1 LIU
FIGURE 27. THE BEHAVIOR OF THE RPOS AND RCLK1 OUTPUT SIGNALS WHILE THE XRT7300 IS TRANSMITTING
SINGLE-RAIL DATA TO THE RECEIVING TERMINAL EQUIPMENT
RPOS
RCLK1
4.0 DIAGNOSTIC FEATURES OF THE XRT7300
The XRT7300 supports equipment diagnostic activi-
ties by supporting the following Loop-Back modes in
the chip:
• Analog Local Loop-Back
• Digital Local Loop-Back
• Remote Loop-Back.
4.1 THE ANALOG LOCAL LOOP-BACK MODE
When the XRT7300 is configured to operate in the
Analog Local Loop-Back Mode, the XRT7300 ignores
any signals that are input to the RTIP and RRING in-
put pins. The Transmitting Terminal Equipment trans-
mits clock and data into the XRT7300 via the TPDA-
TA, TNDATA and TCLK input pins. This data is pro-
cessed through the Transmit Clock Duty Cycle Adjust
PLL and the HDB3/B3ZS Encoder. Finally, this data
outputs to the line via the TTIP and TRING output
pins and is looped back into the AGC/Receive Equal-
izer Block. Consequently, this data is also processed
through the Receive Section of the XRT7300. After
this post-loop-back data has been processed through
the Receive Section it outputs to the Near-End Re-
ceiving Terminal Equipment via the RPOS, RNEG,
RCLK1 and RCLK2 output pins.
Figure 28 illustrates the path that the data takes when
the chip is configured to operate in the Analog Local
Loop-Back Mode.
The XRT7300 can be configured to operate in the An-
alog Local Loop-Back Mode by employing either one
of the following two steps:
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