XRT7300IV View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT7300IV' PDF : 55 Pages View PDF
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Figure 30 illustrates the path that the data takes in the
XRT7300 when the chip is configured to operate in
the Remote Loop-Back Mode.
FIGURE 30. THE REMOTE LOOP-BACK PATH IN THE XRT7300
RLOL EXCLK
XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
RTIP
RRING
REQDIS
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
TTIP
TRING
TXLEV
TXOFF
DMO
AGC/
Equalizer
Slicer
Clock
Recovery
Peak
Detector
LOS Detector
Data
Recovery
Serial
Processor
Interface
Remote
Loop-Back Path
Loop MUX
Invert
HDB3/
B3ZS
Decoder
Pulse
Shaping
HDB3/
B3ZS
Encoder
Device
Monitor
Transmit
Logic
Duty Cycle Adjust
RCLK1
RCLK2/LCV
RPOS
RNEG
DECODIS
RLOS
LLB
RLB
ENCODIS
TAOS
TPDATA
TNDATA
TCLK
MTIP
MRING
During Remote Loop-Back operation, any data which
is inputted via the RTIP and RRING input pins is also
outputted to the Terminal Equipment via the RPOS,
RNEG and RCLK output pins.
The XRT7300 can be configured to operate in the Re-
mote Loop-Back Mode by employing either one of the
following two steps
If the XRT7300 is operating in the HOST Mode:
Access the Microprocessor Serial Interface and write
a “1” into the RLB bit-field and a “0” in the LLB bit-field
in Command Register CR4.
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB RLB
X
X
X
0
1
If the XRT7300 is operating in the Hardware
Mode:
Set the RLB input pin (pin 15) to “High” and the LLB
input pin (pin 16) to “Low”.
39
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