XRT73L03 3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.13
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PRELIMINARY
TABLE 2: ADDRESSES AND BIT FORMATS OF XRT73L03 COMMAND REGISTERS
REGISTER BIT-FORMAT
ADDRESS
COMMAND
REGISTER
TYPE
D4
D3
D2
D1
D0
0x05
CR5-1
R/W
Reserved
Reserved
Reserved Reserved Reserved
0x06
CR6-1
R/W
Reserved
Reserved
Reserved Reserved Reserved
0x07
CR7-1
R/W
Reserved
Reserved
Reserved Reserved Reserved
CHANNEL2
0x08
CR0-2
RO
RLOL2
RLOS2
ALOS2
DLOS2
DMO2
0x09
CR1-2
R/W
TxOFF2
TAOS2
TxClkINV2 TxLEV2
TxBIN2
0x0A
CR2-2
R/W
Reserved ENDECDIS2 ALOSDIS2 DLOSDIS2 REQEN2
0x0B
CR3-2
R/W
SR/(DR)_2 LOSMUT2
RxOFF2 RxClk2INV Reserved
0x0C
CR4-2
R/W
Reserved STS-1/DS3_Ch2 E3_Ch2
LLB2
RLB2
0x0D
CR5-2
R/W
Reserved
Reserved
Reserved Reserved Reserved
0x0E
CR6-2
R/W
Reserved
Reserved
Reserved Reserved Reserved
0x0F
CR7-2
R/W
Reserved
Reserved
Reserved Reserved Reserved
CHANNEL3
0x10
CR0-3
RO
RLOL3
RLOS3
ALOS3
DLOS3
DMO3
0x11
CR1-3
R/W
TxOFF3
TAOS3
TxClkINV3 TxLEV3
TxBIN3
0x12
CR2-3
R/W
Reserved ENDECDIS3 ALOSDIS3 DLOSDIS3 REQEN3
0x13
CR3-3
R/W
SR/(DR)_3 LOSMUT3
RxOFF3 RxClk3INV Reserved
0x14
CR4-3
R/W
Reserved STS-1/DS3_Ch3 E3_Ch3
LLB3
RLB3
0x15
CR5-3
R/W
Reserved
Reserved
Reserved Reserved Reserved
0x16
CR6-3
R/W
Reserved
Reserved
Reserved Reserved Reserved
0x17
CR7-3
R/W
Reserved
Reserved
Reserved Reserved Reserved
Address:
The register addresses presented in the Hexadeci-
mal format.
Type:
The Command Registers are either Read-Only (RO)
or Read/Write (R/W) type of registers.
The default value for each of the bit-fields in these
registers is "0".
a. Operating in the Hardware Mode
To configure individual Channel Data Rate, set the
E3_Ch(n) and the STS-1/DS3_Ch(n) input pins
(where n = 1, 2 or 3) to the appropriate logic states
referenced in Table 3.
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