XRT73L03 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT73L03' PDF : 62 Pages View PDF
XRT73L03 3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.13
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PRELIMINARY
GENERAL DESCRIPTION ................................................................................................. 1
APPLICATIONS ......................................................................................................................................... 1
FEATURES .................................................................................................................................................... 1
Figure 1. XRT73L03 Block Diagram ................................................................................................................. 1
TRANSMIT INTERFACE CHARACTERISTICS ...................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS ........................................................................................................ 2
Figure 2. Pin out of the XRT73L03 in the 14 x 20mm, 0.5mm pitch tqfp .......................................................... 3
ORDERING INFORMATION ............................................................................................... 3
PIN DESCRIPTIONS .......................................................................................................... 4
ELECTRICAL CHARACTERISTICS ................................................................................ 15
Figure 3. Transmit Pulse Amplitude Test Circuit for E3, DS3 and STS-1 Rates (typical channel) ................. 17
Figure 4. Timing Diagram of the Transmit Terminal Input Interface ................................................................ 17
Figure 5. Timing Diagram of the Receive Terminal Output Interface .............................................................. 17
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 21
Figure 6. Microprocessor Serial Interface Data Structure ............................................................................... 22
Figure 7. Timing Diagram for the Microprocessor Serial Interface .................................................................. 22
SYSTEM DESCRIPTION .................................................................................................. 23
THE TRANSMIT SECTION - CHANNELS 1, 2 AND 3 ......................................................................................... 23
THE RECEIVE SECTION - CHANNELS 1, 2 AND 3 ........................................................................................... 23
THE MICROPROCESSOR SERIAL INTERFACE ................................................................................................. 23
TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT73L03 IS OPERATING IN THE HARD-
WARE MODE ....................................................................................................................................... 23
Figure 8. Functional Block Diagram of the XRT73L03 .................................................................................... 24
1.0 Selecting the Data Rate .................................................................................................................... 24
1.1 CONFIGURING CHANNEL(N) .............................................................................................................................. 24
TABLE 2: ADDRESSES AND BIT FORMATS OF XRT73L03 COMMAND REGISTERS ................................................. 24
TABLE 3: SELECTING THE DATA RATE FOR CHANNEL(N) OF THE XRT73L03, VIA THE E3_CH(N) AND STS-1/
DS3_CH(N) INPUT PINS (HARDWARE MODE) ....................................................................................... 26
2.0 The Transmit Section ....................................................................................................................... 26
COMMAND REGISTER CR4-(N) ...................................................................................................... 26
TABLE 4: SELECTING THE DATA RATE FOR CHANNEL(N) OF THE XRT73L03 VIA THE STS-1/DS3_CH(N) AND THE
E3_CH(N) BIT-FIELDS IN THE APPROPRIATE COMMAND REGISTER (HOST MODE) ................................ 26
2.1 THE TRANSMIT LOGIC BLOCK ........................................................................................................................... 26
2.1.1 Accepting Dual-Rail Data from the Terminal Equipment ................................................................ 26
Figure 9. The typical interface for Data Transmission in Dual-Rail Format from the Transmitting Terminal Equip-
ment to the Transmit Section of a channel of the XRT73L03 ....................................................... 27
Figure 10. How the XRT73L03 Samples the data on the TPData and TNData input pins .............................. 27
2.1.2 Configure Channel(n) to accept Single-Rail Data from the Terminal Equipment ........................ 27
COMMAND REGISTER CR1-(N) ....................................................................................................... 27
Figure 11. The Behavior of the TPData and TxClk Input Signals while the Transmit Logic Block is Accepting
Single-Rail Data from the Terminal Equipment ............................................................................. 28
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY .................................................................................. 28
2.3 THE HDB3/B3ZS ENCODER BLOCK ................................................................................................................. 28
2.3.1 B3ZS Encoding ................................................................................................................................... 28
Figure 12. An Example of B3ZS Encoding ..................................................................................................... 29
2.3.2 HDB3 Encoding .................................................................................................................................. 29
Figure 13. An Example of HDB3 Encoding ..................................................................................................... 29
2.3.3 Disabling the HDB3/B3ZS Encoder .................................................................................................. 29
COMMAND REGISTER CR2-(N) ....................................................................................................... 30
2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY ...................................................................................................... 30
Figure 14. The Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications ................... 30
Figure 15. The Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ... 31
2.4.1 Enabling the Transmit Line Build-Out Circuit ................................................................................. 31
COMMAND REGISTER CR1-(N) ....................................................................................................... 31
2.4.2 Disabling the Transmit Line Build-Out Circuit ................................................................................ 31
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