XRT75L00IV View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT75L00IV' PDF : 50 Pages View PDF
REV. 1.0.2
ADDRESS
(HEX)
TYPE
BIT LOCATION
0x04 R/W
D0
D1
D2
D3
D4
D5
0x05 R/W
D0
D1
D2
D3
D4
D5
XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 16: REGISTER MAP DESCRIPTION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
TxLEV Writing a “1” to this bit disables the Transmit Build-out
0
circuit and writing a “0” enables the Transmit Build-out
circuit.
NOTE: See section 4.03 for detailed description.
TxClkINV Writing a “1” to this bit configures the transmitter to
0
sample the data on TPData/TNData input pins on the
rising edge of TxClk.
TAOS Setting this bit to “1” causes a continuous stream of
0
marks to be sent out at the TTIP and TRing pins.
Reserved This Bit Location is Not Used.
INSPRBS Writing a “1” to this bit causes the PRBS generator to
0
insert a single-bit error onto the transmit PRBS data
stream.
NOTE: PRBS Generator/Detector must be enabled
for this bit to have any effect.
TxMON When this bit is set to “1”, the driver monitor is con-
0
nected to its own transmit channel and monitors the
transmit driver. When a transmit failure is detected,
the DMO output will go high.
When this bit is “0”, MTIP and MRing can be con-
nected to other transmit channel for monitoring.
REQEN Setting this bit to “1” enables the Receive Equalizer .
0
NOTE: See section 2.01 for detailed description.
RxMON Writing a “1” to this bit configures the Receiver into
0
monitoring mode. In this mode, the Receiver can
monitor a signal at the RTIP/RRing pins that be atten-
uated up to 20dB flat loss.
LOSMUT Writing a “1” to this bit causes the RPOS/RNEG out-
0
puts to be grounded while the LOS condition is
declared.
NOTE: If this bit has ben set, it will remain set evan
after LOS condition is cleared.
RxClkINV Writing a “1” to this bit configures the Receiver to out-
0
put RPOS/RNEG data on the falling edge of RxClk.
ALOSDIS Writing a “1” to this bit disables the ALOS detector.
0
DLOSDIS Writing a “1” to this bit disables the DLOS detector.
0
41
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