XRT75L00IV View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT75L00IV' PDF : 50 Pages View PDF
XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
0x06 R/W
D0
SR/DR Writing a “1” to this bit configures the Receiver and
0
Transmitter into Single-Rail (NRZ) mode.
D1
STS-1/DS3 Writing a “1” to this bit configures the channel 0 into
0
STS-1 mode.
NOTE: This bit field is ignored if the chip is configured
to operate in E3 mode.
D2
E3
Writing a “1” to this bit configures the chip in E3
0
mode.
D3
LLB
Writing a “1” to this bit configures the chip in Local
0
Loopback mode.
D4
RLB
Writing a “1” to this bit configures the chip in Remote
0
Loopback mode.
D5
0x07 R/W
D0
RLB
0
0
1
1
LLB
Loopback Mode
0
Normal Operation
1
Analog Local
0
Remote
1
Digital
PRBSEN Writing a “1” to this bit enables the PRBS generator/
0
detector.PRBS generator generate and detect either
215-1 (DS3 or STS-1) or 223-1 (for E3).
The pattern generated and detected are unframed
pattern.
JA0
This bit along with JA1 bit configures the Jitter Attenu-
0
ator as shown in the table below.
JA0
JA1
Mode
0
0
16 bit FIFO
0
1
32 bit FIFO
1
0
Disable Jitter
Attenuator
1
1
Disable Jitter
Attenuator
D1
JATx/Rx Writing a “1” to this bit selects the Jitter Attenuator in
0
the Transmit Path. A “0” selects in the Receive Path.
D2
JA1
This bit along with the JA0 configures the Jitter Atten-
0
uator as shown in the table.
D3
PNTRST Setting this bit to “1” resets the Read and Write point-
0
ers of the jitter attenuator FIFO.
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