XRT75L03 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT75L03' PDF : 92 Pages View PDF
XRT75L03
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L03
SDI
SDO
INT
SClk
CS
RESET
HOST/HW
STS-1/DS3_(n)
E3_(n)
REQEN_(n)
RTIP_(n)
RRing_(n)
SR/DR
LLB_(n)
LOSTHR
TTIP_(n)
TRing_(n)
MTIP_(n)
MRing_(n)
DMO_(n)
Serial
Processor
Interface
XRT75L03
XRT75L03
Peak Detector
AGC/
Equalizer
Slicer
Local
LoopBack
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
Jitter
MUX
Attenuator
Remote
LoopBack
Invert
HDB3/
B3ZS
Decoder
Line
Driver
Device
Monitor
Tx
Pulse
Shaping
Tx
Control
Timing
Control
Jitter
Attenuator
MUX
HDB3/
B3ZS
Encoder
Channel 0
Channel 1
Channel 2
CLKOUT
E3Clk,DS3Clk,
STS-1Clk
RLOL_(n)
RxON
RxClkINV
RxClk_(n)
RPOS_(n)
RNEG_(n)/
LCV_(n)
RLB_(n)
RLOS_(n)
JATx/Rx
TPData_(n)
TNData_(n)
TxClk_(n)
TAOS_(n)
TxLEV_(n)
TxON_(n)
Notes: 1. (n) = 0, 1 or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in "Host" Mode and redefined in the "Hardware" Mode.
TRANSMIT INTERFACE CHARACTERISTICS
• Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line
• Integrated Pulse Shaping Circuit
• Built-in B3ZS/HDB3 Encoder (which can be disabled)
• Accepts Transmit Clock with duty cycle of 30%-70%
• Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications
• Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and
ANSI T1.102_1993
• Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE
• Transmitter can be turned off in order to support redundancy designs
RECEIVE INTERFACE CHARACTERISTICS
• Integrated Adaptive Receive Equalization (optional) for optimal Clock and Data Recovery
• Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications
• Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications
• Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications
• Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms
• Built-in B3ZS/HDB3 Decoder (which can be disabled)
• Recovered Data can be muted while the LOS Condition is declared
• Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment
2
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