XRT75L03 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT75L03' PDF : 92 Pages View PDF
XRT75L03
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
GENERAL CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
62
ICT
I In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. For normal operation, set this pin
"High".
NOTE: This pin is internally pulled “High".
70
HOST/HW
I
HOST/Hardware Mode Select:
Tie this pin “High” to configure the XRT75L03 in HOST mode. Tie this “Low” to
configure in Hardware mode.
When the XRT75L03 is configured in HOST mode, the states of many of the dis-
crete input pins are controlled by internal register bits.
NOTE: This pin is internally pulled up.
CONTROL AND ALARM INTERFACE
PIN #
122
SIGNAL NAME
RXA
TYPE
****
DESCRIPTION
External Resistor of 3.01K Ω ± 1%.
Should be connected between RxA and RxB for internal bias.
123
RXB
**** External Resistor of 3.01K Ω ± 1%.
Should be connected between RxA and RxB for internal bias.
JITTER ATTENUATOR INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
44
JA0
I
Jitter Attenuator Select 0:
In Hardware Mode, this pin along with pin 42 configures the Jitter Attenuator as
shown in the table below.
JA0
JA1
0
0
0
1
Mode
16 bit FIFO Depth
32 bit FIFO Depth
1
0
Disable Jitter Attenuator
1
1
Disable Jitter Attenuator
NOTES:
1. The setting of these input pins applies globally to all three (3) channels
in the XRT75L03.
2. This input pin is ignored and should be tied to GND if the XRT75L03 is
configured to operate in the Host Mode.
21
Share Link: 
