XRT75L04 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT75L04' PDF : 57 Pages View PDF
REV. 1.0.4
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 21: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
REGISTER
TYPE
BIT#
NAME
SYMBOL
DESCRIPTION
DEFAULT
VALUE
D0 DMOIS_n This bit is set every time a DMO status change has
0
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
D1 RLOSIS_n This bit is set every time a RLOS status change has
0
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
D2 RLOLIS_n This bit is set every time a RLOL status change has
0
0x02 (ch 0) Reset Interrupt
occurred since the last cleared interrupt. This bit is
0x0A (ch 1) on Status
cleared when the register bit is read.
0x12 (ch 2) Read (source
0x1A (ch 3)
level)
D3 FLIS_n This bit is set every time a FIFO Limit status change
0
has occurred since the last cleared interrupt. This bit
is cleared when the register bit is read.
D4
This bit is set when the PRBS error occurs.
0
PRBSERIS
_n
D5 PRBSERC This bit is set when the PRBS error count register
0
NTIS_n saturates.
D7-D6
Reserved
D0 DMO_n This bit is set when no transitions on the TTIP/
0
TRING have been detected for 128 ± 32 TxCLK
periods.
D1 RLOS_n This bit is set every time the receiver declares an
0
LOS condition.
D2 RLOL_n This bit is set every time when the receiver declares
0
a Loss of Lock condition.
D3
FL_n This bit is set every time the FIFO in the Jitter Atten-
0
uator is within 2 bit of underflow/overflow condition.
D4 ALOS_n This bit is set every time the receiver declares Ana-
0
0x03 (ch 0) Read Alarm Sta-
log LOS condition.
0x0B (ch 1) Only tus
0x13 (ch 2)
D5 DLOS_n This bit is set every time the receiver declares Digi-
0
tal LOS condition.
0x1B (ch 3)
D6 PRBSLS_n This bit is set every time the PRBS detector is not in
0
sync.
D7
Reserved
45
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