XRT75L04 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT75L04' PDF : 57 Pages View PDF
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 21: REGISTER MAP DESCRIPTION
REV. 1.0.4
ADDRESS
(HEX)
REGISTER
TYPE
BIT#
NAME
SYMBOL
DESCRIPTION
DEFAULT
VALUE
D0
JA0_n This bit along with JA1_n bit configures the Jitter
0
Attenuator as shown in the table below.
JA0_n
JA1_n
Mode
0
0
16 bit FIFO
0
1
32 bit FIFO
0x07 (Ch 0) R/W Jitter
0x0F (Ch 1)
Attenuator
0x17 (Ch 2)
1
0
Disable Jitter
Attenuator
1
1
Disable Jitter
Attenuator
0x1F (ch 3)
D1 JATx/Rx_n Setting this bit selects the Jitter Attenuator in the
0
Transmit Path. A “0” selects in the Receive Path.
D2
JA1_n This bit along with the JA0_n configures the Jitter
0
Attenuator as shown in the table.
D3 PNTRST_n Setting this bit resets the Read and Write pointers of
0
the jitter attenuator FIFO.
D4 DFLCK_n Set this bit to “1” to disable fast locking of the PLL.
0
This helps to reduce the time for the PLL to lock to
incoming frequeny when Jitter Attenuator switches
to narrow band.
D7-D5
Reserved
0x30 (Ch 0) RO PRBS
PRBS COUNT REGISTER MSB
0
0x32 (Ch 1)
0x34 (Ch 2)
COUNT
REG
0x36 (ch 3)
0x31 (Ch 0) RO PRBS
PRBS COUNT REGISTER LSB
0
0x33 (Ch 1)
0x35 (Ch 2)
COUNT
REG
0x37 (ch 3)
0x38
RO PRBS
PRBS HOLDING REGISTER
0
HOLDING
REG
0x08
0x10
0x18
Reserved
48
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