XRT79L71 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT79L71' PDF : 441 Pages View PDF
XRT79L71
PRELIMINARY
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
6.3.2.3 DECLARING AND CLEARING THE LOS DEFECT CONDITION ................................................................... 523
6.3.2.4 DECLARING AND CLEARING THE AIS DEFECT CONDITION .................................................................... 525
6.3.2.5 DECLARING AND CLEARING THE FERF/RDI DEFECT CONDITION .......................................................... 527
FIGURE 249. A SIMPLE ILLUSTRATION OF THE NEAR-END TERMINAL EQUIPMENT TRANSMITTING THE FERF/RDI INDICATOR TO THE REMOTE
TERMINAL EQUIPMENT ................................................................................................................................................... 527
6.3.2.6 DETECTING EM BYTE ERRORS .................................................................................................................... 530
6.3.2.7 DETECTING FEBE/REI (FAR-END BLOCK ERROR/REMOTE ERROR INDICATOR) EVENTS ................. 531
6.3.2.8 DETECTING FRAMING BYTE ERRORS ........................................................................................................ 533
6.3.2.9 DECLARING AND CLEARING THE PAYLOAD-TYPE MISMATCH DEFECT CONDITION ................................................. 534
6.3.2.10 MONITORING THE GC BYTE WITHIN THE INCOMING E3 DATA-STREAM ................................................................. 534
6.3.2.11 MONITORING THE NR BYTE WITHIN THE INCOMING E3 DATA-STREAM ................................................................ 534
6.3.3 RECEIVE TRAIL-TRACE MESSAGE CONTROLLER BLOCK ............................................................................... 534
FIGURE 250. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.832 CLEAR-CHANNEL FRAMER MODE (WITH THE RECEIVE TRAIL-TRACE
MESSAGE CONTROLLER BLOCK HIGHLIGHTED) ............................................................................................................... 534
6.3.3.1 AN INTRODUCTION TO TRAIL-TRACE MESSAGES .................................................................................... 534
TABLE 66: THE BYTE-FORMAT OF THE TRAIL-TRACE MESSAGE THAT THIS BEING TRANSPORTED VIA AN E3 DATA-STREAM VIA THE TR BYTE
535
6.3.3.2 CONFIGURING THE XRT79L71 TO RECEIVE TRAIL-TRACE MESSAGES ................................................ 535
6.3.3.3 Receive Trail-Trace Message Controller Block Interrupt ............................................................................ 539
6.3.4 RECEIVE SSM CONTROLLER BLOCK................................................................................................................... 539
FIGURE 251. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.832 CLEAR-CHANNEL FRAMER MODE (WITH THE RECEIVE SSM CONTROL-
LER BLOCK HIGHLIGHTED) ............................................................................................................................................. 540
6.3.4.1 AN INTRODUCTION TO SSM (SYNCHRONIZATION STATUS MESSAGES) .............................................. 540
FIGURE 252. THE BIT-FORMAT OF THE MA-BYTE WITHIN THE E3, ITU-T G.832 FRAMING FORMAT................................................ 540
TABLE 67: THE RELATIONSHIP BETWEEN THE STATES OF BITS 6 AND 7 (WITHIN THE MA BYTE) AND THE EXACT SSM BIT THAT IS BEING
TRANSPORTED VIA BIT 8, WITHIN THE CURRENT MA BYTE .............................................................................................. 541
6.3.4.2 CONFIGURING THE XRT79L71 TO RECEIVE SYNCHRONIZATION STATUS MESSAGES ...................... 541
6.3.4.3 READING OUT THE SSM FROM THE XRT79L71 .......................................................................................... 541
6.3.4.4 RECEIVE SSM CONTROLLER BLOCK INTERRUPTS .................................................................................. 542
TABLE 68: THE RELATIONSHIP BETWEEN THE STATES OF BITS 6 AND 7 (WITHIN THE MA BYTE) AND THE EXACT SSM BIT THAT IS BEING
TRANSPORTED VIA BIT 8, WITHIN THE CURRENT MA BYTE .............................................................................................. 545
6.3.5 RECEIVE LAPD CONTROLLER BLOCK................................................................................................................. 549
FIGURE 253. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.832 CLEAR-CHANNEL FRAMER MODE (WITH THE RECEIVE LAPD CONTROL-
LER BLOCK HIGHLIGHTED) ............................................................................................................................................. 549
FIGURE 254. LAPD MESSAGE FRAME FORMAT ............................................................................................................................ 550
6.3.5.1 RECEIVING STANDARD-TYPE (76 OR 82 BYTE SIZE) LAPD MESSAGES ................................................................. 551
TABLE 69: THE RELATIONSHIP BETWEEN THE CONTENTS WITHIN BITS 4 AND 5 (RXLAPDTYPE[1:0]) AND THE TYPE OF LAPD/PMDL MES-
SAGE RESIDING WITHIN THE RECEIVE LAPD MESSAGE BUFFER ..................................................................................... 555
FIGURE 255. LAPD MESSAGE FRAME FORMAT ............................................................................................................................ 555
FIGURE 256. FLOW-CHART DEPICTING AN APPROACH THAT ONE CAN USE FOR READING OUT THE CONTENTS OF A NEWLY RECEIVED LAPD/
PMDL MESSAGE FROM THE RECEIVE LAPD MESSAGE BUFFER .................................................................................... 557
6.3.5.2 RECEIVING NON-STANDARD VARIABLE LENGTH (E.G., UP TO 82 BYTES) LAPD MESSAGES) ................................ 557
FIGURE 257. FLOW-CHART DEPICTING AN APPROACH THAT ONE CAN USE TO READING OUT THE CONTENTS OF THE NEWLY RECEIVE LAPD/
PMDL MESSAGE FROM THE RECEIVE LAPD MESSAGE BUFFER .................................................................................... 562
6.3.5.3 Receive LAPD Controller Block Interrupt ..................................................................................................... 562
6.3.6 RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK................................................................................ 562
FIGURE 258. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.832 CLEAR-CHANNEL FRAMER MODE (WITH THE "RECEIVE OVERHEAD DATA
OUTPUT INTERFACE" BLOCK HIGHLIGHTED) ................................................................................................................... 563
TABLE 70: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK ..... 564
6.3.6.1 METHOD 1 - OPERATING THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK USING THE "RXOHCLK" METHOD
565
FIGURE 259. ILLUSTRATION OF HOW TO INTERFACE THE "SYSTEM-SIDE TERMINAL EQUIPMENT" TO THE "RECEIVE OVERHEAD DATA OUTPUT
INTERFACE" BLOCK WHEN USING "METHOD 1"................................................................................................................ 566
TABLE 71: RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN THE RXOHCLK SIGNAL, SINCE THE RXOHFRAME SIGNAL
WAS LAST SAMPLED "HIGH" TO THE E3 OVERHEAD BIT THAT IS BEING PROCESSED BY THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK ........................................................................................................................................................ 567
6.3.6.2 OPERATING THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK USING METHOD 2 - THE "RXCLK/RXOHENABLE"
METHOD ................................................................................................................................................................. 568
FIGURE 260. ILLUSTRATION OF HOW TO INTERFACE THE "SYSTEM-SIDE TERMINAL EQUIPMENT" TO THE "RECEIVE OVERHEAD DATA OUTPUT
INTERFACE" BLOCK WHEN USING "METHOD 2"................................................................................................................ 569
TABLE 72: RELATIONSHIP BETWEEN THE NUMBER OF PULSES IN THE "RXOHENABLE" SIGNAL, SINCE THE RXOHFRAME SIGNAL WAS LAST
SAMPLED "HIGH" TO THE E3 OVERHEAD BIT THAT IS BEING OUTPUT (VIA THE RXOH OUTPUT PIN) BY THE RECEIVE OVERHEAD
XV
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