XRT79L71IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT79L71IB' PDF : 441 Pages View PDF
PRELIMINARY
XRT79L71
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
254
FIGURE 109. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE RECEIVE PAYLOAD DATA INPUT
INTERFACE BLOCK OF THE XRT79L71 FOR GAPPED-CLOCK MODE OPERATIONS ........................................................... 256
FIGURE 110. An Illustration of the Behavior of the Receive Payload Data Output Interface Block signals, whenever it has been con-
figured to operate in the "Gapped-Clock" Mode ......................................................................................................... 256
4.3.6.2 NIBBLE-PARALLEL MODE OPERATION OF THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE ............................... 256
FIGURE 111. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE RECEIVE PAYLOAD DATA OUTPUT
INTERFACE BLOCK OF THE XRT79L71 FOR NIBBLE-PARALLEL MODE OPERATION........................................................... 257
FIGURE 112. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR NIBBLE-PARALLEL MODE OP-
ERATION....................................................................................................................................................................... 258
5.0 ARCHITECTURAL/FUNCTIONAL DESCRIPTION OF THE XRT 79L71 - E3, ITU-T G.751 MODE OPER-
ATION .................................................................................................................................................. 259
5.1 DESCRIPTION OF THE E3, ITU-T G.751 FRAME STRUCTURE AND THE OVERHEAD BITS ................ 259
FIGURE 113. ILLUSTRATION OF THE E3, ITU-T G.751 FRAMING FORMAT ...................................................................................... 259
TABLE 35: THE RELATIONSHIP BETWEEN THE CONTENTS OF BITS 2 (FRAME FORMAT) AND 6 (ISDS3) WITHIN THE FRAMER OPERATING MODE
REGISTER, AND THE RESULTING FRAMING FORMAT........................................................................................................ 260
FIGURE 114. A SIMPLE ILLLUSTRATION OF A NEAR-END TERMINAL EXCHANGING E3 DATA WITH A REMOTE TERMINAL, IN AN UN-ERRED MAN-
NER.............................................................................................................................................................................. 262
FIGURE 115. A SIMPLE ILLUSTRATION OF THE NEAR-END TERMINAL TRANSMITTING THE UN-ERRED INDICATION TO THE REMOTE TERMINAL
EQUIPMENT .................................................................................................................................................................. 262
FIGURE 116. A SIMPLE ILLUSTRATION OF A NEAR-END TERMINAL DECLARING THE LOS DEFECT CONDITION WITHIN ITS INCOMING E3 SIGNAL
263
FIGURE 117. A SIMPLE ILLUSTRATION OF THE NEAR-END TERMINAL EQUIPMENT TRANSMITTING THE FERF/RDI INDICATOR TO THE REMOTE
TERMINAL EQUIPMENT ................................................................................................................................................... 263
FIGURE 118. A SIMPLE ILLUSTRATION OF A NEAR-END TERMINAL EXCHANGING E3 DATA WITH A REMOTE TERMINAL, IN AN UN-ERRED MAN-
NER.............................................................................................................................................................................. 264
FIGURE 119. A SIMPLE ILLUSTRATION OF THE NEAR-END TERMINAL TRANSMITTING THE UN-ERRED INDICATION TO THE REMOTE TERMINAL
EQUIPMENT .................................................................................................................................................................. 264
FIGURE 120. A SIMPLE ILLUSTRATION OF A NEAR-END TERMINAL DETECTING BIP-4 NIBBLE ERRORS WITHIN ITS INCOMING E3 SIGNAL265
FIGURE 121. A SIMPLE ILLUSTRATION OF THE NEAR-END TERMINAL EQUIPMENT TRANSMITTING THE FEBE/REI INDICATOR TO THE REMOTE
TERMINAL EQUIPMENT ................................................................................................................................................... 265
5.2 THE TRANSMIT DIRECTION - E3, ITU-T G.751 CLEAR-CHANNEL FRAMER APPLICATIONS ............. 266
FIGURE 122. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT DIRECTION CIRCUITRY WHENEVER THE XRT79L71
HAS BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.751 CLEAR-CHANNEL FRAMER MODE .................................... 266
5.2.1 TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK.................................................................................... 267
FIGURE 123. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT DIRECTION CIRCUITRY, WHENEVER THE XRT79L71
HAS BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.751 CLEAR-CHANNEL FRAMER MODE (WITH THE TRANSMIT PAYLOAD
DATA INPUT INTERFACE BLOCK HIGHLIGHTED) ............................................................................................................... 267
TABLE 36: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ......... 268
TABLE 37: A SUMMARY OF THE "TRANSMIT PAYLOAD DATA INPUT INTERFACE" MODES ................................................................. 271
5.2.1.1 MODE 1 - SERIAL/LOOP-TIMING MODE OPERATION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK . 271
FIGURE 124. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE TRANSMIT PAYLOAD DATA INPUT
INTERFACE BLOCK OF THE XRT79L71 FOR MODE 1 (SERIAL/LOOP-TIMING) OPERATION ................................................ 272
FIGURE 125. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 1 (SERIAL/LOOP-TIM-
ING) MODE OPERATION................................................................................................................................................. 273
5.2.1.2 MODE 2 - SERIAL/LOCAL-TIMING/FRAME SLAVE MODE OPERATION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK ................................................................................................................................................................... 274
FIGURE 126. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 2 (SERIAL/LOCAL-
TIMING/FRAME SLAVE) MODE OPERATION ..................................................................................................................... 274
FIGURE 127. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 2 (SERIAL/LOCAL-TIM-
ING/FRAME SLAVE) MODE OPERATION .......................................................................................................................... 276
5.2.1.3 MODE 3 - SERIAL/LOCAL-TIMING/FRAME MASTER MODE OPERATION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK ................................................................................................................................................................... 276
FIGURE 128. AN ILLUSTRATION AS TO HOW SHOULD INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 3 (SERIAL/
LOCAL-TIMING/FRAME-SLAVE) MODE OPERATION.......................................................................................................... 277
FIGURE 129. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 3 (SERIAL/LOCAL-TIM-
ING/FRAME-MASTER) MODE OPERATION ....................................................................................................................... 278
5.2.1.4 MODE 4 - NIBBLE-PARALLEL/LOOP-TIMING MODE OPERATION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK ................................................................................................................................................................... 279
FIGURE 130. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE TRANSMIT PAYLOAD DATA INPUT
INTERFACE BLOCK OF THE XRT79L71 FOR MODE 4 (NIBBLE-PARALLEL/LOOP-TIMING) OPERATION ................................ 279
FIGURE 131. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 4 (NIBBLE-PARALLEL/
LOOP-TIMING) MODE OPERATION.................................................................................................................................. 281
5.2.1.5 MODE 5 - NIBBLE-PARALLEL/LOCAL-TIMING/FRAME SLAVE MODE OPERATION FOR THE TRANSMIT PAYLOAD DATA INPUT
INTERFACE BLOCK ................................................................................................................................................. 282
FIGURE 132. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 5 (NIBBLE-PARALLEL/
VIII
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