XRT79L71IB View Datasheet(PDF) - Exar Corporation

Part Name

Description

MFG CO.

XRT79L71IB

1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE

Exar Corporation 

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XRT79L71

PRELIMINARY

1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE

REV. P2.0.0

BLOCK ................................................................................................................................................................... 445

FIGURE 212. AN ILLUSTRATION OF HOW TO INTERFACE THE "SYSTEM-SIDE TERMINAL EQUIPMENT" TO THE "TRANSMIT PAYLOAD DATA IN-

PUT INTERFACE" BLOCK (OF THE XRT79L71) FOR MODE 4 (NIBBLE-PARALLEL/LOOP-TIMING) OPERATION...................... 445

FIGURE 213. AN ILLUSTRATION OF THE BEHAVIOR OF THE "SYSTEM-SIDE TERMINAL EQUIPMENT" SIGNALS FOR MODE 4 (NIBBLE-PARALLEL/

LOOP-TIMING) MODE OPERATION.................................................................................................................................. 447

6.2.1.5 MODE 5 - NIBBLE-PARALLEL/LOCAL-TIMING/FRAME SLAVE MODE OPERATION FOR THE TRANSMIT PAYLOAD DATA INPUT

INTERFACE BLOCK ................................................................................................................................................. 447

FIGURE 214. AN ILLUSTRATION OF HOW TO INTERFACE THE "SYSTEM-SIDE TERMINAL EQUIPMENT" SIGNALS FOR MODE 5 (NIBBLE-PARAL-

LEL/LOCAL-TIMING/FRAME SLAVE) MODE OPERATION.................................................................................................... 448

FIGURE 215. AN ILLUSTRATION OF THE BEHAVIOR OF THE "SYSTEM-SIDE TERMINAL EQUIPMENT" SIGNALS FOR MODE 5 (NIBBLE-PARALLEL/

LOCAL-TIMING/FRAME SLAVE) MODE OPERATION .......................................................................................................... 450

6.2.1.6 MODE 6 - NIBBLE-PARALLEL/LOCAL-TIMING/FRAME MASTER MODE OPERATION FOR THE TRANSMIT PAYLOAD DATA IN-

PUT INTERFACE BLOCK ........................................................................................................................................... 450

FIGURE 216. AN ILLUSTRATION OF HOW TO INTERFACE THE "SYSTEM-SIDE TERMINAL EQUIPMENT" SIGNALS FOR MODE 6 (NIBBLE-PARAL-

LEL/LOCAL-TIMING/FRAME MASTER) MODE OPERATION ................................................................................................. 451

FIGURE 217. AN ILLUSTRATION OF THE BEHAVIOR OF THE "SYSTEM-SIDE TERMINAL EQUIPMENT" SIGNALS FOR MODE 6 (NIBBLE-PARALLEL/

LOCAL-TIMING/FRAME MASTER) MODE OPERATION ....................................................................................................... 452

6.2.1.7 OPERATING THE TRANSMIT PAYLOAD DATA INPUT INTERFACE IN THE GAPPED CLOCK MODE .............................. 453

FIGURE 218. AN ILLUSTRATION OF HOW TO INTERFACE THE "SYSTEM-SIDE" TERMINAL EQUIPMENT TO THE "TRANSMIT PAYLOAD DATA IN-

PUT INTERFACE" BLOCK (OF THE XRT79L71) FOR "GAPPED-CLOCK" MODE OPERATIONS............................................... 455

FIGURE 219. AN ILLUSTRATION OF HOW TO INTERFACE THE "SYSTEM-SIDE" TERMINAL EQUIPMENT TO THE "TRANSMIT PAYLOAD DATA IN-

PUT INTERFACE" BLOCK (OF THE XRT79L71) FOR NIBBLE-PARALLEL GAPPED-CLOCK MODE OPERATIONS ..................... 457

6.2.1.8 ACCEPTING AND INSERTING E3 OVERHEAD BYTES VIA THE "TRANSMIT PAYLOAD DATA INPUT INTERFACE" BLOCK 457

6.2.2 TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK ................................................................................. 457

FIGURE 220. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT DIRECTION CIRCUITRY, WHENEVER THE XRT79L71

HAS BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.832 CLEAR-CHANNEL FRAMER MODE (WITH THE TRANSMIT OVERHEAD

DATA INPUT INTERFACE BLOCK HIGHLIGHTED)................................................................................................................ 458

TABLE 58: HOW THE TRANSMIT E3 FRAMER BLOCK INTERNALLY GENERATES EACH OF THE OVERHEAD BITS/BYTES - E3, ITU-T G.832 AP-

PLICATIONS................................................................................................................................................................... 459

TABLE 59: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK ....... 460

6.2.2.1 OPERATING THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK USING METHOD 1 - THE TXOHCLK METHOD 461

FIGURE 221. ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE TRANSMIT OVERHEAD DATA INPUT

INTERFACE BLOCK WHEN USING METHOD 1 ................................................................................................................... 461

TABLE 60: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN THE TXOHCLK SIGNAL, SINCE THE TXOHFRAME SIGNAL

WAS LAST SAMPLED "HIGH" TO THE E3 OVERHEAD BIT THAT IS BEING PROCESSED BY THE TRANSMIT OVERHEAD DATA INPUT

INTERFACE BLOCK ........................................................................................................................................................ 462

FIGURE 222. ILLUSTRATION OF THE SIGNALING THAT MUST OCCUR BETWEEN THE SYSTEM-SIDE TERMINAL EQUIPMENT AND THE TRANSMIT

OVERHEAD DATA INPUT INTERFACE OF THE XRT79L71, IN ORDER TO CONFIGURE THE XRT79L71 TO TRANSMIT THE FERF/RDI

INDICATOR TO THE REMOTE TERMINAL EQUIPMENT (USING METHOD 1)........................................................................... 465

6.2.2.2 OPERATING THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK USING METHOD 2 - THE TXINCLK/TXOHENABLE

METHOD ................................................................................................................................................................. 465

FIGURE 223. ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE TRANSMIT OVERHEAD DATA INPUT

INTERFACE BLOCK WHEN USING METHOD 2 ................................................................................................................... 466

TABLE 61: THE RELATIONSHIP BETWEEN THE NUMBER OF PULSES IN THE TXOHENABLE SIGNAL, SINCE THE TXOHFRAME SIGNAL WAS LAST

SAMPLED "HIGH" TO THE E3 OVERHEAD BIT THAT IS CURRENTLY BEING PROCESSED BY THE TRANSMIT OVERHEAD DATA INPUT

INTERFACE BLOCK ........................................................................................................................................................ 467

FIGURE 224. ILLUSTRATION OF THE SIGNALING THAT MUST OCCUR BETWEEN THE SYSTEM-SIDE TERMINAL EQUIPMENT AND THE TRANSMIT

OVERHEAD DATA INPUT INTERFACE OF THE XRT79L71, IN ORDER TO CONFIGURE THE XRT79L71 TO TRANSMIT THE FERF/RDI

INDICATOR TO THE REMOTE TERMINAL EQUIPMENT (USING METHOD 2)........................................................................... 470

6.2.3 TRANSMIT LAPD CONTROLLER BLOCK .............................................................................................................. 471

FIGURE 225. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT DIRECTION CIRCUITRY, WHENEVER THE XRT79L71

HAS BEEN CONFIGURED TO OPERATE IN THE E3 , ITU-T G.751 CLEAR-CHANNEL FRAMER MODE (WITH THE TRANSMIT LAPD

CONTROLLER BLOCK HIGHLIGHTED) ............................................................................................................................... 471

FIGURE 226. LAPD MESSAGE FRAME FORMAT ............................................................................................................................ 472

TABLE 62: THE LAPD MESSAGE TYPE AND THE CORRESPONDING VALUE OF THE FIRST BYTE, WITHIN THE INFORMATION PAYLOAD FOR

STANDARD 76 OR 82 BYTE MESSAGES ........................................................................................................................... 473

6.2.3.1 TRANSMITTING STANDARD-TYPE (76 OR 82 BYTE SIZE) LAPD MESSAGES ........................................................... 473

TABLE 63: A MAPPING OF THE VALUE TO BE WRITTEN INTO INDIRECT ADDRESS LOCATION 0X11B0 AND THE CORRESPONDING PMDL MES-

SAGE............................................................................................................................................................................ 478

FIGURE 227. -FLOW-CHART DEPICTING AN APPROACH THAT ONE CAN USE TO WRITING THE PAYLOAD PORTION OF THE LAPD/PMDL MES-

SAGE INTO THE TRANSMIT LAPD MESSAGE BUFFER...................................................................................................... 479

6.2.3.2 TRANSMITTING NON-STANDARD VARIABLE LENGTH (E.G., UP TO 82 BYTES) LAPD MESSAGES ............................ 481

FIGURE 228. FLOW-CHART DEPICTING AN APPROACH THAT ONE CAN USE TO WRITING IN THE REMAINING BYTES OF THE OUTBOUND MES-

SAGE INTO THE TRANSMIT LAPD MESSAGE BUFFER...................................................................................................... 485

6.2.3.3 Transmit LAPD Controller Block Interrupt ................................................................................................... 488

6.2.4 TRANSMIT TRAIL-TRACE MESSAGE CONTROLLER BLOCK ............................................................................ 488

XIII

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