XRT83SL216 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL216' PDF : 42 Pages View PDF
REV. 1.0.0
BIT
D2
D1
D0
XRT83SL216
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 7: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION
NAME
GLOBAL CONTROL REGISTER FOR ALL 16 CHANNELS (0X00H)
FUNCTION
Register
Type
Default
Value
(HW reset)
JABW
JA Band width Select
This bit is used to select the band with of the JA PLL.
R/W
0
"0" = 10 Hz "1" = 1.5Hz
NOTE: If a "1" is written into this bit, JA FIFO size of 64 bit wide is
automatically selected.
JASEL1 Jitter Attenuator Select
R/W
0
JASEL0 These bits are used to configure the Jitter Attenuator into the
0
Receive or Transmit path.
"00" = Disabled
"01" = Transmit Path
"10" = Receive Path
"11" = Disabled
TABLE 8: MICROPROCESSOR REGISTERS 0X01H &0X02H BIT DESCRIPTION
INTERRUPT STATUS REGISTERS (0X01H) & 0X02H
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
INTS_n Interrupt Status
RO
0
D6
These 2 registers are ready only to determine when an interrupt
0
D5
event occurs, the channel that generates interrupt can be identified
0
D4
with minimum read/write operation.
0
D3
0
D2
0
D1
0
D0
0
31
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