XRT83SL216 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL216' PDF : 42 Pages View PDF
REV. 1.0.0
XRT83SL216
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 11: MICROPROCESSOR REGISTER BIT DESCRIPTION
CHANNEL CONTROL REGISTER (CHANNEL_n, where n = 0:15)
(0X06H, 0X09H, 0X0CH, 0X0FH, 0X12H, 0X15H, 0X18H, 0X1BH, 1EH, 0X21H, 0X24H, 0X27H, 0X2AH, 0X2DH, 0X30H, 0X33H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D5
ATAOS_n Automatic Transmit All Ones
R/W
0
If ATAOS_n is selected, an all ones pattern will be transmitted from
TTIP/TRING if the channel experiences an RLOS condition. If
RLOS does not occur, ATAOS_n will remain inactive.
"0" = Disabled
"1" = Enabled
D4
TAOS_n Transmit All Ones
R/W
0
If TAOS_n is selected, an all ones pattern will be transmitted from
TTIP/TRING if the transmitter is turned on. Remote Loop Back
has priority over TAOS.
"0" = Disabled
"1" = Enabled
D3
RLAM_n RLOS/AIS Mode Select for channel n
R/W
0
This bit is used to select the industry standard for declaring / clear-
ing RLOS and AIS functionality. See the Receive section of the
Line Interface description.
"0" = ITU G.775
"1" =ETSI300233
D2
TXOE_n Transmit Output Enable
R/W
0
Upon power up, the tranmitters are tri-stated. This bit is used to
enable the transmitter for this channel if the TxOE pin is pulled
"High". If the TxOE pin is pulled "Low", all 8 transmitters are tri-
stated.
"0" = Transmitter is disabled
"1" = Transmitter is enabled if TxOE pin is pulled "High"
D1
RCLKinv_n Receiver Clock Invert
R/W
0
This bit is used to invert receive clock update edge with respect to
0
RPOS/RNEG output data.
"0" =RPOS/RNEG data is updated on the rising edge of RCLK
"1" =RPOS/RNEG data is updated on the falling edge of RCLK.
D0
TCLKinv_n Transmit Clock Invert
R/W
0
This bit is used to invert transmit clock sampling edge with respect
to TPOS/TNEG input data.
"0" =TPOS/TNEG data is sampled on the falling edge of TCLK
"1" =TPOS/TNEG data is sampled on the rising edge of TCLK.
33
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