XRT83SL216IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL216IB' PDF : 41 Pages View PDF
XRT83SL216
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 6: MICROPROCESSOR REGISTER DESCRIPTION
REG ADDR TYPE
D7
D6
D5
D4
D3
D2
Channel 14 Control Register (0x2Eh - 0x30h)
48
0x30 R/W SRES_14 * ARAOS_14 ATAOS_14
49
0x31 R/W Reserved
AISIE_14
DMOIE_14
50
0x32 RUR/ Reserved
RO
AISIS_14
DMOIS_14
Channel 15 Control Register (0x31h - 0x33h)
TAOS_14
RLOSIE_14
RLOSIS_14
RLAM_14
Reserved
Reserved
TXOE_14
Reserved
AISS_14
51
0x33 R/W SRES_15 * ARAOS_15 ATAOS_15 TAOS_15
RLAM_15
TXOE_15
52
0x34 R/W Reserved
AISIE_15
DMOIE_15 RLOSIE_15 Reserved
Reserved
53
0x35 RUR/ Reserved
RO
AISIS_15
DMOIS_15 RLOSIS_15 Reserved
AISS_15
REV. 1.0.0
D1
D0
RCLKinv_14 TCLKinv_14
LPB1
LPB0
DMOS_14 RLOSS_14
RCLKinv_15 TCLKinv_15
LPB1
LPB0
DMOS_15 RLOSS_15
NOTE: * Indicates that these bits are WRITE-ONLY Reset for that channel register only.
TABLE 7: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION
GLOBAL CONTROL REGISTER FOR ALL 16 CHANNELS (0X00H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
GIE Global Interrupt Enable
R/W
0
The global interrupt enable is used to enable/disable all interrupt
activity for all 16 channels. This bit must be set "High" for the inter-
rupt pin to operate.
"0" = Disable all interrupt generation
"1" = Enable interrupt generation to the individual channel registers
D6
Reserved This Register Bit is Not Used
R/W
0
D5
SR/DR Single Rail / Dual Rail Select
R/W
0
This bit is used to configure the receive outputs and transmit inputs
to single rail or dual rail data formats.
"0" = Dual Rail
"1" = Single Rail
D4
CODE Encoding / Decoding Select (Single Rail Mode Only)
This bit is used to select between AMI or HDB3.
R/W
0
"0" = HDB3
"1" = AMI
D3
FIFOS FIFO Depth Select
R/W
0
The FIFO depth select is used to configure the part for a 32-bit or
64-bit FIFO (Within the Jitter Attenuator Block). The delay of the
FIFO is typically equal to ½ the FIFO depth.
"0" = 32-bit FIFO
"1" = 64-bit FIFO
30
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