XRT83SL216IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL216IB' PDF : 41 Pages View PDF
XRT83SL216
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 9: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION
REV. 1.0.0
REVISION "ID" REGISTER (0X03H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Revision The revision "ID" of the XRT83SL216 LIU is used to enable soft-
RO
0
D6
"ID" ware to identify which revision of silicon is currently being tested.
0
D5
The revision "ID" for the first revision of silicon (Revision A) will be
0
D4
0x01h.
0
D3
0
D2
0
D1
0
D0
1
TABLE 10: MICROPROCESSOR REGISTERS 0X04H & 0X05H BIT DESCRIPTION
DEVICE "ID" REGISTERS (0X04H & 0X05H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Device "ID" The device for this chip consists of 2 read only registers. The ID for
RO
D6
the XR T83SL216 is 0x8004h.
D5
D4
D3
D2
D1
D0
TABLE 11: MICROPROCESSOR REGISTER BIT DESCRIPTION
CHANNEL CONTROL REGISTER (CHANNEL_n, where n = 0:15)
(0X06H, 0X09H, 0X0CH, 0X0FH, 0X12H, 0X15H, 0X18H, 0X1BH, 1EH, 0X21H, 0X24H, 0X27H, 0X2AH, 0X2DH, 0X30H, 0X33H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
SRES_n Software Reset
WO
X
Writing a "1" to this bit will cause the channel register to reset to
it's default value.
NOTE: This is a Write-Only bit.
D6
ARAOS_n Automatic Receive All Ones
R/W
0
If ARAOS_n is selected, an all ones pattern will be sent to the
RPOS/RNEG outputs if the channel experiences an RLOS condi-
tion. If RLOS does not occur, ARAOS_n will remain inactive.
"0" = Disabled
"1" = Enabled
32
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