XRT83SL28 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL28' PDF : 47 Pages View PDF
XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
xr
REV. 1.0.0
NAME
PIN
RNEG/LCV7
60
RNEG/LCV6
64
RNEG/LCV5
117
RNEG/LCV4
121
RNEG/LCV3
49
RNEG/LCV2
45
RNEG/LCV1
136
RNEG/LCV0
132
RTIP7
75
RTIP6
87
RTIP5
94
RTIP4
106
RTIP3
34
RTIP2
22
RTIP1
15
RTIP0
3
RRING7
76
RRING6
86
RRING5
95
RRING4
105
RRING3
33
RRING2
23
RRING1
14
RRING0
4
TXOE
9
DMO7
73
DMO6
72
DMO5
109
DMO4
108
DMO3
36
DMO2
37
DMO1
144
DMO0
1
TCLK7
69
TCLK6
66
TCLK5
115
TCLK4
112
TCLK3
40
TCLK2
43
TCLK1
138
TCLK0
141
TYPE
O
Same as Host Mode.
DESCRIPTION
I
Same as Host Mode.
I
Same as Host Mode.
I
Transmit Output Enable (Global Pin for All 8 Channels)
Upon power up, the transmitters are tri-stated. Enabling the transmitters is
controlled by pulling the TXOE hardware pin "High". If the TxOE pin is pulled
"Low", all 8 transmitters are tri-stated.
NOTE: TxOE is ideal for redundancy applications. See the Redundancy
Applications Section of this datasheet for more details. Internally
pulled "Low" with a 50KΩ resistor.
O
Same as Host Mode.
I
Transmit Clock Input
TCLK is the input facility clock used to sample the incoming TPOS/TNEG data.
If TCLK is pulled "Low" for 16 MCLK cycles, the transmitter outputs at TTIP/
TRING are tri-stated. If TCLK is pulled "High" for 16 MCLK cycles, the trans-
mitter outputs at TTIP/TRING will send an All Ones pattern. TPOS/TNEG data
can be sampled on either edge of TCLK selected by the TCLKinv pin.
NOTE: The TCLKinv pin is a global setting that applies to all 8 channels.
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