XRT83SL28ES View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL28ES' PDF : 47 Pages View PDF
xr
REV. 1.0.0
XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 7: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION
GLOBAL CONTROL REGISTER FOR ALL 8 CHANNELS (0X00H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
GIE Global Interrupt Enable
R/W
0
The global interrupt enable is used to enable/disable all interrupt
activity for all 8 channels. This bit must be set "High" for the inter-
rupt pin to operate.
"0" = Disable all interrupt generation
"1" = Enable interrupt generation to the individual channel registers
D6
SR/DR Single Rail / Dual Rail Select
R/W
0
This bit is used to configure the receive outputs and transmit inputs
to single rail or dual rail data formats.
"0" = Dual Rail
"1" = Single Rail
D5
CODE Encoding / Decoding Select (Single Rail Mode Only)
This bit is used to select between AMI or HDB3.
R/W
0
"0" = HDB3
"1" = AMI
D4
RCLKinv Receiver Clock Data
R/W
0
"0" = RPOS/RNEG data is updated on the rising edge of RCLK
"1" = RPOS/RNEG data is updated on the falling edge of RCLK
D3
TCLKinv Transmitter Clock Data
R/W
0
"0" = TPOS/TNEG data is sampled on the falling edge of TCLK
"1" = TPOS/TNEG data is sampled on the rising edge of TCLK
D2
FIFOS FIFO Depth Select
R/W
0
The FIFO depth select is used to configure the part for a 32-bit or
64-bit FIFO (Within the Jitter Attenuator Block). The delay of the
FIFO is typically equal to ½ the FIFO depth.
"0" = 32-bit FIFO
"1" = 64-bit FIFO
D1
JASEL1 Jitter Attenuator Select
R/W
0
D0
JASEL0 These bits are used to configure the Jitter Attenuator into the
0
Receive or Transmit path.
"00" = Disabled
"01" = Transmit Path
"10" = Receive Path
"11" = Disabled
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