XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.8
PRELIMINARY
TABLE 34: MICROPROCESSOR REGISTER #15, BIT DESCRIPTION .......................................................... 60
TABLE 35: MICROPROCESSOR REGISTER #64, BIT DESCRIPTION .......................................................... 61
CLOCK SELECT REGISTER ........................................................................................... 62
Figure 23. Register 0x81h Sub Registers ...................................................................................... 62
TABLE 36: MICROPROCESSOR REGISTER #65, BIT DESCRIPTION .......................................................... 63
TABLE 37: MICROPROCESSOR REGISTER #66, BIT DESCRIPTION .......................................................... 64
ELECTRICAL CHARACTERISTICS ................................................................................ 66
TABLE 38: ABSOLUTE MAXIMUM RATINGS ........................................................................................... 66
TABLE 39: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS ........................................ 66
TABLE 40: XRT83SL34 POWER CONSUMPTION .................................................................................. 66
TABLE 41: E1 RECEIVER ELECTRICAL CHARACTERISTICS ..................................................................... 67
TABLE 42: T1 RECEIVER ELECTRICAL CHARACTERISTICS ..................................................................... 68
TABLE 43: E1 TRANSMIT RETURN LOSS REQUIREMENT ........................................................................ 68
TABLE 44: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................... 69
TABLE 45: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................... 69
Figure 24. ITU G.703 Pulse Template ............................................................................................. 70
TABLE 46: TRANSMIT PULSE MASK SPECIFICATION .............................................................................. 70
Figure 25. DSX-1 Pulse Template (normalized amplitude) ........................................................... 71
TABLE 47: DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS ........................................... 71
TABLE 48: AC ELECTRICAL CHARACTERISTICS .................................................................................... 72
Figure 26. Transmit Clock and Input Data Timing ........................................................................ 72
MICROPROCESSOR INTERFACE I/O TIMING .................................................................................................. 73
Intel Interface Timing - Asynchronous ....................................................................................................... 73
Figure 27. Receive Clock and Output Data Timing ....................................................................... 73
Figure 28. Intel Asynchronous Programmed I/O Interface Timing .............................................. 73
TABLE 49: ASYNCHRONOUS MODE 1 - INTEL 8051 AND 80188 INTERFACE TIMING ............................... 74
Motorola Asychronous Interface Timing .................................................................................................... 75
Figure 29. Motorola 68K Asynchronous Programmed I/O Interface Timing .............................. 75
TABLE 50: ASYNCHRONOUS - MOTOROLA 68K - INTERFACE TIMING SPECIFICATION ............................. 75
Figure 30. Microprocessor Interface Timing - Reset Pulse Width ............................................... 75
ORDERING INFORMATION ............................................................................................. 76
PACKAGE DIMENSIONS - 14X20 MM, 128 PIN PACKAGE ................................................................................ 76
REVISIONS ................................................................................................................................................. 77
III