XRT83SL34 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL34' PDF : 80 Pages View PDF
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.8
PRELIMINARY
FIGURE 27. RECEIVE CLOCK AND OUTPUT DATA TIMING
RDY
RCLKR
RCLKF
RCLK
RPOS
or
RNEG
RHO
MICROPROCESSOR INTERFACE I/O TIMING
INTEL INTERFACE TIMING - ASYNCHRONOUS
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum ex-
ternal glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency,
and with the timings of x86 or i960 family or microprocessors. The interface timing shown in Figure 28 and
Figure 30 is described in Table 49.
FIGURE 28. INTEL ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING
ALE_AS
A D D R [6 :0 ]
CS
D A T A [7 :0 ]
RD_DS
W R _R /W
RDY_DTACK
t0
t5
t1
READ OPERATION
Valid Address
Valid Data for Readback
t2
WRITE OPERATION
t0
t5
Valid Address
Data Available to W rite Into the LIU
t3
t4
73
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