PRELIMINARY
XRT83VSH28
REV. P1.0.0
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
2.2 Clock and Data Recovery
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. This allows for multi-
channels to arrive from different timing sources and remain independent. In the absence of an incoming
signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered data can
be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To update data
on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register. Figure 6 is a timing diagram
of the receive data updated on the rising edge of RCLK. Figure 7 is a timing diagram of the receive data
updated on the falling edge of RCLK. The timing specifications are shown in Table 4.
FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK
RDY
RCLKR
RCLKF
RCLK
RPOS
or
RNEG
R OH
FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK
RDY
RCLKF
RCLKR
RCLK
RPOS
or
RNEG
ROH
TABLE 4: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG
PARAMETER
SYMBOL
MIN
TYP
MAX
RCLK Duty Cycle
RCDU
45
50
55
Receive Data Setup Time
RSU
150
-
-
Receive Data Hold Time
RHO
150
-
-
RCLK to Data Delay
RDY
-
-
40
RCLK Rise Time (10% to 90%)
RCLKR
-
with 25pF Loading
-
40
RCLK Fall Time (90% to 10%)
RCLKF
-
with 25pF Loading
-
40
NOTE: VDD=3.3V ±5%, TA=25°C, Unless Otherwise Specified
UNITS
%
ns
ns
ns
ns
ns
22