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XRT83VSH28IB-F View Datasheet(PDF) - Exar Corporation

Part Name
Description
MFG CO.
XRT83VSH28IB-F
Exar
Exar Corporation Exar
'XRT83VSH28IB-F' PDF : 74 Pages View PDF
XRT83VSH28
PRELIMINARY
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. P1.0.0
2.2.1 Receive Sensitivity
To meet short haul requirements, the XRT83VSH28 can accept E1 signals that have been attenuated by 12dB
of flat loss. However, the XRT83VSH28 can tolerate cable loss and flat loss beyond the industry specifications.
The receive sensitivity in the short haul mode is approximately 1,800 feet without experiencing bit errors, LOF,
pattern synchronization, etc. Although data integrity is maintained, the RLOS function (if enabled) will report an
RLOS condition according to the receiver loss of signal section in this datasheet. The test configuration for
measuring the receive sensitivity is shown in Figure 8.
FIGURE 8. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY
W&G ANT20
Network
Analyzer
Tx
Cable Loss
Rx
E1 = PRBS 215 - 1
Rx
Flat Loss
XRT83VSH28
External Loopback
8-Channel
Tx
Short Haul LIU
2.2.2 Interference Margin
The interference margin for the XRT83VSH28 is -15db. The test configuration for measuring the interference
margin is shown in Figure 9.
FIGURE 9. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN
E1 = 1,024kHz
Sinewave
Generator
E1 = PRBS 215 - 1
W&G ANT20 Tx
Network
Analyzer
Rx
Flat Loss
Cable Loss
Rx
External Loopback
XRT83VSH28
Tx
8-Channel LIU
2.2.3 General Alarm Detection and Interrupt Generation
The receive path detects RLOS, AIS, QRPD and FLS. These alarms can be individually masked to prevent the
alarm from triggering an interrupt. To enable interrupt generation, the Global Interrupt Enable (GIE) bit must be
set "High" in the appropriate global register. Any time a change in status occurs (it the alarms are enabled), the
interrupt pin will pull "Low" to indicate an alarm has occurred. Once the status registers have been read, the
INT pin will return "High". The status registers are Reset Upon Read (RUR). The interrupts are categorized in
a hierarchical process block. Figure is a simplified block diagram of the interrupt generation process.
NOTE: The interrupt pin is an open-drain output that requires a 10kexternal pull-up resistor.
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