XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
TRANSMIT SERIAL DATA INPUT
(Framer Channel Number indicated by _n)
REV. 1.0.1
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
TxSerClk_0
TxSerClk_1
TxSerClk_2
TxSerClk_3
TxSerClk_4
TxSerClk_5
TxSerClk_6
TxSerClk_7
D8
A16
D20
G23
Y23
AC18
AD9
AC6
I or O
Transmit Serial Clock Signal --Transmit Framer_n:
This clock signal is used by the Transmit payload data Input Interface, to latch
the contents of the TxSer_n signal into the Octal T1/E1/J1 Framer IC. Data
that is applied at the TxSer_n input is latched into the Transmit payload data
Input Interface (for Framer_n) on either the rising edge or the falling edge of
TxSerClk_n depending on configurations of Framer_n. TxSerClk_n can either
be an input or an output.
DS1 Mode:
Transmit Back-plane Interface-1.544 MHz Clock Mode
If TxMUXEN = 0 and TxIMODE[1:0] = 00 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking data at a rate of 1.544
Mbit/s. If the Transmit Section of Framer_n has been configured to use the
TxSerClk_n signal as the timing source, then this signal will be an Input. If the
Transmit Section of Framer_n has been configured to use either the
RxLineClk_n signal or the OSCClk signal as the timing source, then
TxSerClk_n will be an Output.
Transmit Back-plane Interface-High Speed Clock Mode
If TxMUXEN ≠ 0 and TxIMODE[1:0] ≠ 00 in Transmit interface control register,
Transmit back-plane interface of Framer_n is operating at a high-speed mode
and is taking data at rates of 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, 12.352
Mbit/s or 16.384 Mbit/s. The TxSerClk_n signal will be an Input clock signal
running at 1.544 MHz.
E1 Mode:
Transmit Back-plane Interface-2.048 MHz Clock Mode
If TxMUXEN = 0 and TxIMODE[1:0] = 00 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking data at a rate of 2.048
Mbit/s. If the Transmit Section of Framer_n has been configured to use the
TxSerClk_n signal as the timing source, then this signal will be an Input. If the
Transmit Section of Framer_n has been configured to use either the
RxLineClk_n signal or the OSCClk signal as the timing source, then
TxSerClk_n will be an Output.
Transmit Back-plane Interface-High Speed Clock Mode
If TxMUXEN ≠ 0 or TxIMODE[1:0] ≠ 00 in Transmit interface control register,
Transmit back-plane interface of Framer_n is operating at a high-speed mode.
The TxSerClk_n signal will be an Input clock signal running at 2.048 MHz.
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