XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
TRANSMIT SERIAL DATA INPUT
(Framer Channel Number indicated by _n)
REV. 1.0.1
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
TxMSync_0
TxMSync_1
TxMSync_2
TxMSync_3
TxMSync_4
TxMSync_5
TxMSync_6
TxMSync_7
C6
B13
A22
F26
AC26
AF21
AF10
AE6
I or O
Multiframe Sync Pulse Input/Output—Framer_n:
This signal indicates the boundary of an outbound multi-frame.
DS1 Mode:
Transmit Back-plane Interface-1.544 MHz Clock Mode
If TxMUXEN = 0 and TxIMODE[1:0] = 00 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking data at a rate of 1.544
Mbit/s. This pin is configured to be an Input if the TxSerClk_n input pin is con-
figured to be the timing reference for the Transmit section of Framer_n. Con-
versely, this pin will be configured as an Output if the RxLineClk input pin or
the OSCClk input pins are configured to be the timing reference for the Trans-
mit section of Framer_n.The roles of these pins when configured as input or
output, is described below.
When pin is configured to be an Input
If this pin is configured to be an input, this pin must be pulsed "High" for one
period of TxSerClk_n, the instant that the Transmit payload data Interface (of
Framer_n) is processing the first bit of a DS1 Multi-frame.
NOTE: It is imperative that the TxMSync_n input signal be synchronized with
the TxSerClk_n input signal.
When pin is configured to be an Output
If this pin is configured to be an output, then it will pulse "High", for one period
of TxSerClk_n, when the Transmit payload data Input Interface (of Framer_n)
is processing the last bit of a DS1 Multi-frame.
E1 Mode:
Transmit Back-plane Interface-2.048 MHz Clock Mode
If TxMUXEN = 0 and TxIMODE[1:0] = 00 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking data at a rate of 2.048
Mbit/s. This pin is configured to be an Input if the TxSerClk_n input pin is con-
figured to be the timing reference for the Transmit section of Framer_n. Con-
versely, this pin will be configured as an Output if the RxLineClk input pin or
the OSCClk input pins are configured to be the timing reference for the Trans-
mit section of Framer_n.
When pin is configured to be an Input
If this pin is configured to be an input, this pin must be pulsed "High" for one
period of TxSerClk_n, the instant that the Transmit payload data Interface (of
Framer_n) is processing the first International Bit (Si) of an "outbound" CRC
payload data Multiframe.
NOTES:
1. This pin is ignored if CRC Multiframe Alignment has been disabled.
2. It is imperative that the TxMSync_n input signal be synchronized with
the TxSerClk_n input signal.
When pin is configured to be an Output
If this pin is configured to be an output, then it will pulse "High", for one period
of TxSerClk_n, when the Transmit payload data Input Interface (of Framer_n)
is processing the last bit, within an "outbound" CRC Multi-frame.
NOTES:
1. This pin is inactive if CRC Multi-frame Alignment has been disabled.
2. The purpose of this output pin is to permit the Terminal Equipment to
maintain alignment with the "outbound" CRC-Multi-frame structure.
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