XRT91L34IV-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L34IV-F' PDF : 38 Pages View PDF
REV. 1.0.1
XRT91L34
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
TABLE 16: MICROPROCESSOR INTERFACE REGISTER 0X09, 0X11, 0X19, 0X21 BIT DESCRIPTION
CONFIGURATION AND INTERRUPT ENABLE CHANNEL REGISTER (CH0 = 0X09, CH1 = 0X11, CH2 = 0X19, CH3 = 0X21)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved This Register Bit is Not Used
RO
0
D6
Reserved This Register Bit is Not Used
RO
0
D5 DATAnRATE1 Data Rate Selection Bit-1 and Bit-0
R/W
0
D4
DATAnRATE0
These bits selects SONET/SDH reception speed rate for each of
the four channels independently according to the logic below.
R/W
0
DATANRATE[1:0]
0
0
0
1
1
0
1
1
DATA RATE
STS-1/STM-0
51.84 Mbps
STS-3/STM-1
155.52 Mbps
STS-12/STM-4
622.08 Mbps
STS-12/STM-4
622.08 Mbps
D3
Reserved This Register Bit is Not Used
D2
Reserved This Register Bit is Not Used
D1
LOLn_IE Loss of Lock Interrupt Enable
"0" = Masks the LOL interrupt generation
"1" = Enables Interrupt generation
D0
LOSn_IE Loss of Signal Interrupt Enable
"0" = Masks the LOS interrupt generation
"1" = Enables Interrupt generation
NOTE: n denotes channel number.
RO
0
RO
0
R/W
0
R/W
0
31
Share Link: 
