XRT91L34IV-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L34IV-F' PDF : 38 Pages View PDF
XRT91L34
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
TABLE 17: MICROPROCESSOR INTERFACE REGISTER 0X0A, 0X12, 0X1A, 0X22 BIT DESCRIPTION
INTERRUPT STATUS CONTROL REGISTER (CH0 = 0X0A, CH1 = 0X12, CH2 = 0X1A, CH3 = 0X22)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved This Register Bit is Not Used
RO
0
D6
Reserved This Register Bit is Not Used
RO
0
D5
LOLn Loss of Lock Detection
RO
0
The Loss of Lock Detect is used to indicate whether the CDR PLL
is locked.
"0" = CDR Locked
"1" = CDR Out of Lock
D4
LOSn Loss of Signal
The LOS indicates the Loss of Signal activity.
"0" = No Alarm
"1" = A LOS condition is present
RO
0
D3
Reserved This Register Bit is Not Used
RO
0
D2
Reserved This Register Bit is Not Used
RO
0
D1
LOLn_IS Loss of Lock Interrupt Status
RUR
0
An external interrupt will not occur unless the LOLn_IE interrupt
enable bit is set in the appropriate registers 0x09, 0x11, 0x19, and
0x21 for channels 0, 1, 2, and 3 respectively.
"0" = No Change
"1" = Change in CDR Lock Status Occurred
D0
LOSn_IS Loss of Signal Interrupt Status
RUR
0
An external interrupt will not occur unless the LOSn_IE interrupt
enable bit is set in the appropriate registers 0x09, 0x11, 0x19, and
0x21 for channels 0, 1, 2, and 3 respectively.
"0" = No Change
"1" = Change in LOS Status Occurred
NOTE: n denotes channel number.
32
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