Z51F0410HCX View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z51F0410HCX' PDF : 184 Pages View PDF
Z51F0410
Product Specification
4.3.4 Watch Dog Timer Register description
The Watch dog timer (WDT) Register consists of Watch Dog Timer Register (WDTR), Watch Dog
Timer Counter Register (WDTCR) and Watch Dog Timer Mode Register (WDTMR).
4.3.5 Register description for Watch Dog Timer
WDTR (Watch Dog Timer Register:Write Case) : 8EH
7
WDTR7
W
6
WDTR 6
W
5
WDTR 5
W
4
WDTR 4
W
3
WDTR 3
W
2
WDTR 2
W
1
0
WDTR 1
WDTR 0
W
W
Initial value : FFH
WDTR[7:0] Set a period
WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTR Value+1)
Note) To guarantee proper operation, the data should be greater than 01H.
WDTCR (Watch Dog Timer Counter Register:Read Case) : 8EH
7
WDTCR 7
R
6
WDTCR 6
R
5
WDTCR 5
R
4
WDTCR 4
R
3
WDTCR 3
R
2
WDTCR 2
R
WDTCR[7:0] WDT Counter
1
0
WDTCR 1 WDTCR 0
R
R
Initial value : 00H
WDTMR (Watch Dog Timer Mode Register) : 8DH
7
6
5
4
3
2
WDTEN WDTRSON WDTCL
WCKDIV1 WCKDIV0
-
R/W
R/W
R/W
R/W
R/W
-
1
0
-
WDTIFR
-
R/W
Initial value : 00H
WDTEN Control WDT operation
0
disable
1
enable
WDTRSON Control WDT Reset operation
0
Free Running 8-bit timer
1
Watch Dog Timer Reset ON
WDTCL Clear WDT Counter
0
Free Run
1
Clear WDT Counter (auto clear after 1 Cycle)
WCKDIV[1:0] WDT Clock Division Selection
00
Default No Divided
01
WDT Clock = BIT Clock / 2
10
WDT Clock = BIT Clock / 4
11
WDT Clock = BIT Clock / 8
WDTIFR When WDT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write
‘0’ to this bit or auto clear by INT_ACK signal.
0
WDT Interrupt no generation
1
WDT Interrupt generation
PS029502-0212
PRELIMINARY
75
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