Z801808PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z801808PSC' PDF : 85 Pages View PDF
Z80180
Microprocessor Unit
73
Control Register (OMCR) can be programmed to select between certain differences between
the Z80 and the 64180.
Operating Control OMCR: I/O Address = 3Eh)
D7 D6 D5 — — — — —
Reserved
IOC (R/W)
M1TE (W)
M1E (R/W)
Figure 76. Operating Control Register (OMCR: I/O Address = 3Eh
M1E (M1 Enable)—This bit controls the M1 output and is set to a 1
during reset.
When M1E = 1, the M1 output is asserted Low during the opcode fetch cycle, the INT0
acknowledge cycle, and the first machine cycle of the NMI acknowledge.
On the Z80180, this choice makes the processor fetch a RETI instruction one time only, and
when fetching a RETI from zero-wait-state memory, uses three clock machine cycles which
are not fully Z80-timing compatible, but are compatible with the on-chip CTCs.
When MIE = 0, the processor does not drive M1 Low during instruction fetch cycles. After
fetching a RETI instruction one time only with normal timing, the processor refetches the
instruction using fully Z80-compatible cycles that include driving M1 Low. As a result,
some external Z80 peripherals may require properly decoded RETI instruction.
T1 T2 T3 T1 T2 T3 TI TI TI T1 T2 T3 TI T1 T2 T3 TI
φ
A0–A18 (A19)
D0–D7
PC
EDh
PC+1
4Dh
PC
PC+1
EDh
4Dh
M1
MREQ
RD
ST
Figure 77. RETI Instruction Sequence with MIE=0
PS014004-1106
Architecture
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