Z80195_ View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z80195_' PDF : 326 Pages View PDF
Z 8018x Fam ily
M PU Us e r M anual
30
inserted depending on the programmed value in IWI1 and IWI0. Refer to
Table 4.
Table 4. Wait State Insertion
Th e Num be r of W ait State s
IW I1
For e xte rnal
I/O re gis te rs
IW I0 acce s s e s
For INT1, For NM I
INT2 and
inte rrupt
For INT0
inte rnal
ack now le dge
For inte rnal inte rrupt
inte rrupts cycle s
I/0
ack now le dge ack now le dge w h e n M 1 is
re gis te rs cycle s w h e n cycle s
Low
acce s s e s M 1 is Low (Note 2)
(Note 2)
0
0
1
0
2
2
0
0
1
2
(Note 1)
4
1
0
3
5
1
1
4
6
Note:
1. For Z8X180 internal I/O register access (I/O addresses 0000H-003FH), IWI1 and IWI0 do not
determine wait state (TW) timing. For ASCI, CSI/O and PRT Data Register accesses, 0 to 4 Wait States
(TW) are generated. The number of Wait States inserted during access to these registers is a function of
internal synchronization requirements and CPU state. All other on-chip I/O register accesses (that is,
MMU, DMAC, ASCI Control Registers, for instance.) have no Wait States inserted and thus require only
three clock cycles.
2. For interrupt acknowledge cycles in which M1 is High, such as interrupt vector table read and PC
stacking cycle, memory access timing applies.
WAIT Input and RESET
During RESET, MWI1, MWI0 IWI1 and IWI0, are all 1, selecting the
maximum number of Wait States (TW) (three for memory accesses, four
for external I/O accesses).
UM005001-ZMP0400
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