Z80195_ View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z80195_' PDF : 326 Pages View PDF
Z 8018x Fam ily
M PU Us e r M anual
35
SLP 2nd Op Code
Fetch Cycle
T2 T3 T1
Phi
SLEEP mode
T2 TS TS
Op Code Fetch or Interrupt
Acknowledge Cycle
T1 T2 T3
INT1, NMI
A0–A19 SLP 2nd Op Code address
FFFFFH
HALT
M1
Figure 21. SLEEP Timing Diagram
IOSTOP Mode
IOSTOP mode is entered by setting the IOSTOP bit of the I/O Control
Register (ICR) to 1. In this case, on-chip I/O (ASCI, CSI/O, PRT) stops
operating. However, the CPU continues to operate. Recovery from
IOSTOP mode is by resetting the IOSTOP bit in ICR to 0.
SYSTEM STOP Mode
SYSTEM STOP mode is the combination of SLEEP and IOSTOP modes.
SYSTEM STOP mode is entered by setting the IOSTOP bit in ICR to 1
followed by execution of the SLP instruction. In this mode, on-chip I/O
and CPU stop operating, reducing power consumption. Recovery from
SYSTEM STOP mode is the same as recovery from SLEEP mode, noting
that internal I/O sources, (disabled by IOSTOP) cannot generate a
recovery interrupt.
UM005001-ZMP0400
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