Z8622912PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8622912PSC' PDF : 52 Pages View PDF
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Note: OSD and XDS display modes always have Enhanced At-
tributes enabled.
D6–ODRP. This bit selects the Drop Shadow or Full Box
mode in the OSD and XDS displays (High = DROP SHAD-
OW and Low = BOX). The default is High.
D7–O15. This bit selects the number of TV lines per char-
acter row in the OSD and XDS display modes (High = 15
lines/row and Low = 13 lines/row). The default is High.
H Position Register Address = 02h
with a base row of 12, this register should be set to C8h. If
the value of the x and y bits result in a display where Text
rows are off the top of the screen, then the first row of the
Text display starts in row 1, having the number of rows de-
termined by the x value.
Line 21 Activity Register Address = 04h
Bit D7 D6 D5 D4 D3 D2 D1 D0
res res res res res res XDS SCH
RR
Figure 23. Line 21 Activity Register (Address = 04h)
Bit D7 D6
BLUBX HPO
R/W R/W
D5
h5
R/W
D4
h4
R/W
D3
h3
R/W
D2
h2
R/W
D1 D0
h1 h0
R/W R/W
Figure 21. H Position Register (Address = 02h)
D0–D5–h0–h5. This bit is used to set the Horizontal Timing
of the display. The default value in this register is 26h. Each
count change represents an incremental timing change of
330 ns. Decreasing the value of this field moves the display
to the RIGHT. Conversely, increasing the value of this field
moves the display to the LEFT.
D6–HPO. This bit sets the polarity to be used for locking to
the HIN signal when in the EXT HLK mode (Low = Rising
Edge, High = Falling Edge). The default is Low.
D7–BLUBX. This bit designates the color of BOX (High =
Blue Box and Low = Black Box). The default is Low.
Text Position Register Address = 03h
Bit D7 D6 D5 D4 D3 D2 D1 D0
y3 y2 y1 y0 x3 x2 x1 x0
R/W R/W R/W R/W R/W R/W R/W R/W
Figure 22. Text Position Register (Address = 03h)
D0–D3–x0–x3. This bit sets the Number Of Rows in the Text
display. The default is 15 rows.
D4–D7–y0–y3. This bit sets the Base Row of the Text dis-
play.
The default value in this register is set to FFh, which pro-
duces a 15-row display with base row 15. Entering a new
value in this register can alter the size and placement of the
Text display. For example, to produce an 8-row Text display
D0–SCH. This bit indicates data being processed in the Data
Channel selected for display. The display becomes inactive
if no data is received for the selected channel within the pre-
vious 16 seconds (High = Active, Low = Inactive). The reset
state is Low.
D1–XDS. This bit indicates that XDS data is being pro-
cessed. The display becomes inactive if no XDS data is re-
ceived within the previous 16 seconds (High = Active, Low
= Inactive). The reset state is Low.
D2–D7. Reserved.
XDS Filter Register Address = 05h
Bit D7
s2
R/W
D6
s1
R/W
D5
D4 D3 D2 D1
D0
s0 PUBL MISC CHAN FUTR CURR
R/W R/W R/W R/W R/W R/W
Figure 24. XDS Filter Register (Address = 05h)
D0–CURR. This bit selects the Current Class packets for
output through the Serial Control port when XDS recovery
has been enabled.
D1–FUTR. This bit selects the Future Class packets for out-
put through the Serial Control port when XDS recovery has
been enabled.
D2–CHAN. This bit selects the Channel Information Class
packets for output through the Serial Control port when
XDS recovery has been enabled.
D3–MISC. This bit selects the Miscellaneous Class packets
for output through the Serial Control port when XDS re-
covery has been enabled.
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