Z8622912PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8622912PSC' PDF : 52 Pages View PDF
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D4–PUBL. This bit selects Public Service Class packets for
output through the Serial Control port when XDS recovery
has been enabled.
D5–D7–s0–s2. This bit selects a set of secondary parame-
ters, tabulated below, to be used in filtering the XDS data
when XDS recovery has been enabled.
Table 17. XDS Secondary Filter Settings1
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Notes:
1. Setting this register to 00h turns XDS data recovery off.
Setting bits D0 through D4 enables XDS recovery for the
classes selected, as qualified by the secondary filter (bits
D5–D7). If bits D0–D4 are all set to “1”, all classes of XDS
data will be output, even the reserved and undefined
classes.
2. The Time Information includes the Time of Day (TOD) and
Local Time Zone (LTZ) packets.
3. The VCR Information selects TOD, LTZ, Net ID, Local Call
Letters, Impulse Capture, Tape Delay, Composite 2, and
Out-of-Band Channel Number packets for recovery.
ZiLOG
D3–dLOK. Active High, indicating that the state of the
LOCK signal has changed. The SS register must be read to
determine the current state.
D4–dSCH. Active High, indicating that a change in selected
channel activity has occurred. The Line 21 Activity register
must be read in order to determine if the selected data chan-
nel is active.
D5–dXDS. Active High, indicating that a change in XDS ac-
tivity has occurred. The Line 21 Activity register must be
read to determine if XDS data is active.
D5–dXDS. Active High, indicating that a change in XDS ac-
tivity has occurred. The Line 21 Activity register must be
read to determine if XDS data is active.
D6–dCAP. Active High, indicating that a change in a cap-
tion data channel activity has occurred. The Caption Activ-
ity Register (Address 08h) must be read to determine ex-
actly which caption channels are now active.
D7–dTXT. Active High, indicating that a change in a Text
data channel activity has occurred. The Caption Activity
Register (Address 08h) must be read to determine exactly
which text channels are now active.
Note: Except as noted for the case of D1 and D2 above, the mas-
ter device must write a 1 to the appropriate bit in the In-
terrupt Request Register to clear the Interrupt. Writing a
1 to any valid bit position, the Interrupt Request Register
is equivalent to CLEARing a interrupt request on that bit.
Interrupt Request Register Address = 06h
Bit D7 D6 D5 D4 D3 D2 D1 D0
dTXT dCAP dXDS dSCH dLOK EOF DLE res
R/W R/W R/W R/W R/W R R R
Figure 25. Interrupt Request Register (Address = 06h)
Interrupt Mask Register Address = 07h
Bit D7 D6 D5 D4 D3 D2
dTXT dCAP dXDS dSCH dLOK EOF
R/W R/W R/W R/W R/W R/W
D1
DLE
R/W
D0
DAV
R/W
Figure 26. Interrupt Mask Register Address = 07h
D0–res. Reserved.
D1–DLE. Active High, indicating that the data line has end-
ed. This bit clears in each field a few lines after row 15.
D2–EOF. Active High, indicating that the video signal is
currently at the end of a field. This bit clears in each field
a few lines after row 15.
This register identifies which activities in the Interrupt Re-
quest Register are used to cause an interrupt. Setting a bit
to a 1 enables the interrupt when the corresponding event
becomes active. Setting all bits of this register to zero dis-
ables interrupts. The Caption Activity Register Address =
08h.
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