Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
Interrupts. The Z86E7X has five different interrupts. The
interrupts are maskable and prioritized (Figure 42). The
five sources are divided as follows: three sources are
claimed by Port 3 lines P33-P31, the remaining two by the
counter/timers (Table 10). The Interrupt Mask Register
globally or individually enables or disables the five inter-
rupt requests.
IRQ0 IRQ2
IRQ 1, 3, 4
Interrupt
Edge
Select
IRQ Register (D6, D7)
IRQ
IMR
5
Interrupt
Request
Global
Interrupt
Enable
IPR
Priority
Logic
Vector Select
Figure 37. Interrupt Block Diagram
1-46
PRELIMINARY
DS96LVO1100