Z86E7216PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86E7216PSC' PDF : 74 Pages View PDF
Z86E72/E73
OTP IR Microcontrollers
HALT. HALT turns off the internal CPU clock, but not the HALT) mode, it is necessary to first flush the instruction
XTAL oscillation. The counter/timers and external inter- pipeline to avoid suspending execution in mid-instruction.
1 rupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active. To do this, the user must execute a NOP (opcode = FFH)
The devices are recovered by interrupts, either externally immediately before the appropriate sleep instruction, i.e.,
or internally generated. An interrupt request must be exe-
cuted (enabled) to exit HALT mode. After the interrupt ser-
FF NOP ; clear the pipeline
vice routine, the program continues from the instruction af-
6F STOP ; enter STOP mode
ter the HALT.
or
FF NOP ; clear the pipeline
STOP. This instruction turns off the internal clock and ex-
7F HALT ; enter HALT mode
ternal crystal oscillation and reduces the standby current
to 10 µA (typical) or less. STOP mode is terminated only Port Configuration Register (PCON). The PCON regis-
by a reset, such as WDT time-out, POR, SMR, or external ter configures the comparator output on Port 3. It is locat-
reset. This causes the processor to restart the application ed in the expanded register file at Bank F, location 00 (Fig-
program at address 000CH. In order to enter STOP (or ure 44).
PCON (0F) 0H
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Reserved (Must be 1)
Figure 39. Port Configuration Register (PCON)
(Write Only)
Comparator Output Port 3 (D0). Bit 0 controls the com-
parator used in Port 3. A 1 in this location brings the com-
parator outputs to P34 and P37, and a 0 releases the Port
to its standard I/O configuration.
Stop-Mode Recovery Register (SMR). This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 46). All bits are write only ex-
cept bit 7, which is read only. Bit 7 is a flag bit that is hard-
ware set on the condition of STOP recovery and reset by
a power-on cycle. Bit 6 controls whether a low level or a
high level is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits D2, D3, and D4, of
the SMR register, specify the source of the Stop-Mode Re-
covery signal. Bit D0 determines if SCLK/TCLK are divided
by 16 or not. The SMR is located in Bank F of the Expand-
ed Register Group at address 0BH
DS96LVO1100
PRELIMINARY
1-49
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