Z86M1720ASC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86M1720ASC' PDF : 138 Pages View PDF
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
70
EEPROM Register
Address: SELECT 2Ch
Name: Interface Configuration Register 4
Type: Read/Write
Table 54. Interface Configuration Register 4: Address 2Ch
Bit Placement Bit Name
Bit 2-0
TSTCLK
Bit 3
EN_POLL_BSY
Bit 4
Bit 5
EN_GLOB_INT
EN_PC_INT5
Bit 6
EN_BVD_INPUTS
Description
These power management clock select bits can be used to
provide delay times in a number of different scales.
Table 55 describes the different delay scale settings. Also
see Register 2Ah (Table 53).
This bit allows the ZX6017 to poll the Busy status bit in
the local controller task file. When enabled in PCMCIA
ATA I/O mode, the Busy status bit in the local controllers
task file latches into the pin replacement register. In
PCMCIA ATA Memory mode, the Busy status bit is placed
on the Ready/Busy signal. Set this bit to 1 to enable auto
polling. When this bit is cleared, auto polling is disabled.
On Power-On Reset, it is set to 0.
This is a Global Interrupt Enable for the M-PINT pin.
When set to 1, this bit enables the local µP interrupts.
When cleared, it disables the local µP interrupt. On Power-
On Reset, it is set to 0.
This bit enables the local Processor interrupt when the
PCMCIA host has written the I/O event indication Register
CCR4. This interrupt source stays present until this bit is
set to 0. When set to 1, this bit is active. On Power-On
Reset, it is set to 0.
When set to 1, this bit enables the two BVD inputs to be
reflected either in Pin Replacement Register or on the
corresponding pins of the ZX6017. On Power-On Reset, it
is set to 0. See also Register 0Ch (Table 66).
PS012002-1201
Programming Internal Registers
Share Link: 
