1EDI2004AS View Datasheet(PDF) - Infineon Technologies
Part Name
Description
MFG CO.
'1EDI2004AS' PDF : 138 Pages View PDF
EiceDRIVERTM SIL
1EDI2004AS
Functional Description
In case of a hard reset condition on the secondary side, the behavior of the pin of the device is defined in
Table 17.
Table 17 Pin behavior (secondary side) in case of reset condition
Pin
Output Level Comments
TON
TOFF
DESAT
Low (VEE2)
Low (VEE2)
Low (GND2)
Passive Clamping
Passive Clamping
Clamped.
GATE
DACLP
NUV2
Low (VEE2)
High (VREG2)
Low (GND2)
Passive Clamping
Active clamping disabled by default.
AMCLP
High (VREG2) Miller Clamping enabled by default.
VREG
VREG2 typ.
if VCC2 > 6V typ.1)
1) For more information see Table 55.
2.4.11 Operation in Configuration Mode
This section describes the mechanisms to configure the device.
2.4.11.1 Static Configuration Parameters
Static parameters can be configured when the device is in Mode OPM2 by writing the appropriate register.
Once Mode OPM2 is left with the SPI Command EXIT_CMODE, the configuration parameters are frozen on both
primary and secondary chips. This means in particular that write accesses to the corresponding registers are
invalidated. This prevents static configurations to be modified during runtime. Besides, the configuration
parameters on the primary and secondary side are protected with a memory protection mechanism. In case
the values are not consistent, a Reset Event and / or an Event Class B is generated.
2.4.11.1.1 Configuration of the SPI Parity Check
The SPI interface supports by default an odd parity check. The Parity Check mechanism (active at the
reception of an SPI word) can be disabled by setting bit PCFG.PAREN to 0B. Setting bit PAREN to 1B enables the
Parity Check.
Parity Bit Generation for the transmitter can not be disabled.
2.4.11.1.2 Configuration of the VBE Compensation
The VBE compensation of signal TON and TOFF can be activated or deactivated by writing bit SCFG.VBEC. See
Chapter 2.4.6 for more details.
Data Sheet
51
Rev. 2.0
2019-01-16
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