1EDI2004AS View Datasheet(PDF) - Infineon Technologies
Part Name
Description
MFG CO.
'1EDI2004AS' PDF : 138 Pages View PDF
EiceDRIVERTM SIL
1EDI2004AS
Functional Description
2.4.6.2 Switching Sequence Description
Figure 15 shows an idealized switching sequence. When a valid turn-on command is detected, a certain
propagation time tPDON is needed by the logic to transfer the PWM command to the secondary side. At this
point the TTOFF delay time tTTOFF defined by bit field SRTTOF.RTVAL is added before the turn-on command is
executed. Signal TON is then activated, while signal TOFF is deactivated.
When a valid turn-off command is detected, a certain propagation time tDOFF is needed by the command to be
processed by the logic on the secondary side. This propagation time depends on the event having generated
the turn-off action (non exhaustive list):
• In case of a PWM turn-off command at pin INP, tDOFF=tPDOFF.
• In case of a DESAT Event, tDOFF=tOFFDESAT2.
• In case of an OCP event, tDOFF=tOFFOCP2.
• In case of an Event Class A on the primary side: tDOFF=tOFFCLA.
• In case of an Event Class B on the secondary side: tDOFF=tOFFCLB2.
Note:
The timing tDOFF doesn’t consider the SCFG.AMCLD setting (Figure 16). The regular turn-on/off
processing will be delayed by the SCFG.AMCLD value if setting is > 0 (refer to Table 59).
When the turn-off command is processed by the logic, signal DACLP is deactivated (i.e. active clamping is
enabled). Signal TON and TOFF are decreased with the slew rate tSLEW fixed by hardware. Once the voltage at
pin TOFF has reached the value defined by bit field SRTTOF.GPR(or SSTTOF.GPS in the case of a safe turn-off),
the turn-off sequence is interrupted. Time tTTOFF is defined as the moment when the device starts turning off
signal TOFF, and the moment where the turn-off sequence is resumed. Depending on the event that triggered
the turn-off sequence, tTTOFF is given by either bit field SRTTOF.RTVAL or SSTTOF.STVAL. Once the TTOFF time
has elapsed, a hard commutation takes place, and signals TON and TOFF are driven to VEE2.
Note:
Once a turn-off sequence is started, it is completed to the end with the same delay parameters.
At the moment when the hard commutation takes place, signal DACLP remains deactivated for time tACL
defined by bit field SACLT.AT. When this time is elapsed, signal DACLP is reactivated (i.e. active clamping is
disabled).
In case SACLT.AT is set to 0H, DACLP is constantly activated (constant High level). In case SACLT.AT is set to FFH,
DACLP is constantly at Low level.
Data Sheet
41
Rev. 2.0
2019-01-16
Share Link: 
