1EDI2004AS View Datasheet(PDF) - Infineon Technologies
Part Name
Description
MFG CO.
'1EDI2004AS' PDF : 138 Pages View PDF
EiceDRIVERTM SIL
1EDI2004AS
Functional Description
2.4.9 Internal Supervision
The Internal Supervision functionality is summarized in Table 13:
Table 13 System Supervision Overview
Parameter
Short Description
Function
Monitoring of the key internal functions of the chip.
Periodicity
Continuous.
Action in case of failure event See below
Programmability
No.
In-System Testability
No.
The primary and secondary chips are equipped with internal verification mechanisms ensuring that the key
functions of the device are operating correctly. The internal blocks which are supervised are listed below:
• Lifesign watchdog: mutual verification of the response of both chips (both primary and secondary).
• Oscillators (both primary and secondary, including open / short detection on signals IREF1 and IREF2).
• Memory error (both primary and secondary).
2.4.9.1 Lifesign watchdog
The primary and the secondary chips monitor each other by the mean of a lifesign signal. The periodicity of
the lifesign is typically tLS. Each chip expects a lifesign from its counterpart within a given time window. In case
a lifesign error is detected by a chip, a reset event is generated on both sides (lead to OPM0) as well as NFLTB
pin is set. Dueto communication loss on both sides both bits PER.CER1 and SER.CER2 are set.
Note:
Bits PER.CER1 and SER.CER2 indicate a loss of communication event. The current status of the
internal communication is indicated by bit PSTAT.SRDY.
2.4.9.2 Oscillator Monitoring
The main oscillators on the primary and on the secondary side are monitored continuously. Two distinct
mechanisms are used for this purpose:
• Lifesign Watchdog allows to detect significant deviations from the nominal frequency (both primary and
secondary, see above).
• Open / short detection on pin IREF1.
• Open detection on pin IREF2.
In case a failure is detected on pin IREF1, the primary chip is kept in reset state for the duration of the failure
and signal NRST/RDY is asserted, This leads to the detection of a lifesign error by the secondary chip,
generating thus a reset event.
In case a failure is detected on pin IREF2, an Emergency (regular) Turn-Off sequence is initiated. The secondary
chip is kept in reset state for the duration of the failure. This leads to the detection of a lifesign error by the
primary chip, generating thus a reset event.
Data Sheet
47
Rev. 2.0
2019-01-16
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