EiceDRIVERTM SIL
1EDI2004AS
Functional Description
2.4.6.3 Active Miller Clamping Transistor Clamping
The device can be configured to generate via pin AMCLP a control signal for an external Miller clamp transistor.
During turn-off, when the gate signal reaches a voltage below VGATE1L, AMCLP goes high.
At turn-on, in order to avoid the risk of cross-current in the output stage of the device, a delay can be generated
in order to delay the PWM control signal (Figure 16). The delay is configured via bit field SCFG.AMCLD.
INP
5V
GND2
VTOFF /
VTON
tTTOFF
tPDON
tAMCDel
tAMCDel
tDOFF
tTTOFF
time
VGATE
VCC2
VGATE2
VGPOFx
VGATE1
VEE2
5V
90%
VAMCL
10%
GND2
tfa llAM C L P
Figure 16 AMCLP operation
Data Sheet
43
time
time
tAMCOFFDel
triseAMCLP time
Rev. 2.0
2019-01-16